Theo J. Powell

Delta Iddq for testing reliability

Point defects, which cause small current increases and potentially early failures, can be masked by increased chip background currents at elevated temperatures. The difficulty of screening point defects will likely also occur in denser geometries. Delta Iddq is shown to help distinguish between early fail and reliable chips at these elevated temperatures. Memory application demonstrates that a variety of delta Iddq tests can screen early fail defects.

Analysis and simulation of parallel signature analyzers

Abstract Parallel signature analyzers (PSAs) implemented as multiple input linear feedback shift registers are very useful in compressing test response data in digital circuits. In this paper, some analytical results on error detection using a class of PSAs are presented. The concept of monitoring the most significant bit of a PSA is introduced. Finally, a PASCAL simulator, called SIGLYZER, to study the effectiveness of PSAs in detecting errors in test response data, is described. The use of the SIGLYZER as a design tool is also explained.

Bist for deep submicron asic memories with high performance application

Today’s ASIC designs consist of more memory in terms of both area and number of instances. The shrinking of geometries has an even greater effect upon memories due to their tight layouts. These two trends are putting much greater demands upon memory BIST requirements. At-speed testing and custom test algorithms are becoming essential for insuring overall product quality. At-speed testing on memories that now operate in the 10 to 800 MHz range can be a challenge. Another demand upon memory BIST is determining the location of defects so that the cause can be diagnosed, or repaired with redundant cells. A tool and methodology that meets these difficult requirements is discussed.

Chasing subtle embedded RAM defects for nanometer technologies

A designs increasing density, as well as its number of embedded memories increases its vulnerability to a variety of potential manufacturing defects. Standard March test algorithms used for obtaining good defect coverage must be augmented by new algorithms that target defects not screened by embedded BIST controllers. This paper presents our experience diagnosing address decode open faults (ADOF) using scan patterns. Subsequently, tests were added in the BIST controller to target ADOF. Other tests were added to screen potential bit/byte write-enable faults in memories with bit/byte write-enable controls

Test generation and design for test for a large multiprocessing DSP

The TMS320C80 is a programmable, parallel processing DSP. The test approach was an engineering mix of design for testability, test view creation, and verification. This mixture facilitated timely test generation and had other important benefits. We document the overall test methodology and the benefits derived therein.

A 256 Meg SDRAM BIST for disturb test application

The Disturb Test Algorithms are targeted for row adjacent coupled defects that can be time elapsed dependent. A BIST design is described for application of these tests for testing 256 Meg SDRAM chips.

Testability features in the TMS370 family of microcomputers

The TMS370 family of microcomputers was designed with a requirement for >99% stuck fault coverage. A design for testability (DFT) methodology called parallel/serial scan design was used which partitioned the design into independently testable modules along functional divisions. The automatically generated tests are then reuseable when the same functional module is included in a different configuration of microcomputer by simply concatenating the module tests. Thus, test preparation is only needed once per module. The DFT methodology is presented along with the application results.<<ETX>>

Consistently dominant fault model for tristate buffer nets

Unknown values result from floating and contention type faults on tristate buffer nets thereby causing MISR signature loss during test pattern compression. A Consistently Dominant Fault model is presented that removes the problem and permits fault detection of several problem tristate buffer stuck faults.

Correlating defects to functional and I/sub DDQ/ tests

Functional tests and I/sub DDQ/ tests are studied to determine their effectiveness toward screening failures. A model is presented for curve fitting correlation data between fault coverages and defect quality employing the Williams and Brown defect level to fault coverage equation. The model is used for multiple test types. Empirical data were gathered to demonstrate its effectiveness over functional and I/sub DDQ/ tests. I/sub DDQ/ test data demonstrates two categories of I/sub DDQ/ defects: pattern sensitive and pattern insensitive defects.

Reducing design verification cycle time through testbench redundancy

Design flows for modern-day system-on-chip (SoC) designs focus on reducing the design cycle time, but not on design verification time. Nearly 70% of SoC design cycle time is consumed by design verification (Raynaud, 2003). Most functional verification happens through simulation. This paper proposes a technique by which the simulation times of time consuming verification steps can be reduced. The proposed technique exploits the testbench redundancy during functional simulations to reduce simulation time. We demonstrate how the testbench redundancy can be exploited to gain valuable cycle time during memory BIST simulations.