Thirumalai Sridhar

Method and apparatus for testing very large scale integrated memory circuits

Apparatus for testing high density VLSI memory elements of a semiconductor chip having bit line connections to at least selected ones of which includes a parallel signature analyzer built onto the chip adjacent the memory elements and connected to at least some of them by the bit line connections. The parallel signature analyzer is configurable to apply selected signals onto the bit lines in one mode to enable test signals to be written into selected memory cells to generate preselected memory states therewithin. The parallel signature analyzer is also configurable, in another mode to read the states of the memory cells and to develop a signature of the states read to indicate whether the selectively applied signals were properly written into and read from the high density memory. Means are also provided for delivering the signature to an output lead in the form of a quotient bit, if desired.

A New Parallel Test Approach for Large Memories

Memory test times¿and thus test costs¿are increasing rapidly as the size of the memories grows each year. Testability techniques therefore must be developed to reduce the test time without compromising the test quality. This article presents an approach that meets this goal using parallel signature analyzers (PSAs). PSAs can access more data cells in parallel than I/O pins can, and the approachs parallelism reduces the test time. The proposed method is analyzed with respect to test time, test quality, and silicon area penalty.

Analysis and simulation of parallel signature analyzers

Abstract Parallel signature analyzers (PSAs) implemented as multiple input linear feedback shift registers are very useful in compressing test response data in digital circuits. In this paper, some analytical results on error detection using a class of PSAs are presented. The concept of monitoring the most significant bit of a PSA is introduced. Finally, a PASCAL simulator, called SIGLYZER, to study the effectiveness of PSAs in detecting errors in test response data, is described. The use of the SIGLYZER as a design tool is also explained.

Design of easily testable bit-sliced systems

Bit-sliced systems are formed by interconnecting identical slices or cells to form a one-dimensional iterative logic array (ILA). This paper presents several design techniques for constructing easily testable bit-sliced systems. Properties of ILAs that simplify their testing are examined. C-testable ILAs, which require a constant number of test patterns independent of the array size, are characterized, and a method for making an arbitrary ILA C-testable is presented. A new testability concept for arrays called I-testability is introduced. I-testability ensures that identical test responses can be obtained from every cell in an ILA, and thus simplifies response verification. I-testable ILAs are characterized, as well as Cl-testable arrays, which are simultaneously C- and I-testable. A method of making an arbitrary ILA Cl-testable is presented. The application of C- and I-testing to the design of bit-sliced (micro-) computers is investigated. For this purpose a family of easily testable processor slices is described. The design of a self-testing CPU based on I-testing is discussed, and compared with a more conventional self-testing design.