Theodore G. Tessier
Motorola
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Featured researches published by Theodore G. Tessier.
electronic components and technology conference | 1992
Theodore G. Tessier; Gerry Chandler
A scanning laser ablation based via generation process for use in MCM-D (multichip module-D) substrate fabrication is described. The robustness of a variety of thin (1-5 mu m-thick) conformal metal masking layers was compared by static exposure with a computer-controlled XeCl excimer laser exposure tool. The relative ablation rates of commercially available dielectric materials were compared for a range of fluences from 0 to 600 mJ/cm/sup 2/ using static excimer laser exposure. Based on process limits established by these static test results, generic scanning laser ablation processing parameters were established which were successfully used for the fabrication of vias in low stress, acetylene terminated and fluorinated polyimides as well as benzocyclobutene (BCB) and polyphenylquinoxalines (PPQs). The extent of soot accumulation during scanning laser ablation was dependent on the conformal metal masking layer used. In some cases, excessive accumulation of soot resulted in mask cracking around the vias. The use of helium as a process gas was found to dramatically reduce the amount of soot that accumulated and consequently eliminated soot related mask damage. >
electronic components and technology conference | 1994
A.J.G. Strandjord; Robert Heistand; J.N. Bremmer; Philip Garrou; Theodore G. Tessier
As Multichip Module (MCM) technology has evolved from research to commercial production, cost has become the important issue for implementation. Manufacturing schemes are incorporating those processes and materials which take advantage of the most cost effective technologies to meet the specific performance requirements for a given application. The work described in this paper demonstrates how laminate based MCM technology (MCM-L) and deposited dielectric technology (MCM-D) can be combined to form a low cost solution for systems requiring high density interconnections. The use of laminate board technology to fabricate the relatively low density interconnect portion of the multilayer structure, allows one to take advantage of the well established and highly cost competitive printed wiring board (PWB) industry. Deposited dielectric technology takes advantage of the high density capabilities, normally associated with MCM-D packaging, to increase performance. Benzocyclobutene (BCB) is a well suited dielectric material for a laminate/deposited dielectric application (MCM-LD) since it can be cured at relatively low temperatures (220-275/spl deg/C). Additionally, the use of BCB as the interlayer dielectric provides a stable copper/BCB interface, excellent planarization over rough topographies, and exhibits very low moisture absorption. Several low cost processing techniques were demonstrated as part of this MCM-LD program. These include an inherently photosensitive BCB formulation as the thin film dielectrics, meniscus coating as the large area deposition process for the photosensitive-BCB, and an in-line belt furnace for Rapid Thermal Curing (RTC). A two layer module was fabricated to demonstrate the feasibility of this MCM-LD process flow. This paper describes the processing issues and techniques associated with such a hybridized interconnection technology.<<ETX>>
electronic components and technology conference | 1993
Theodore G. Tessier; E.G. Myszka
This paper outlines strategies to cost reduce MCM-D substrate fabrication. A simplification of an existing excimer laser via generation process is outlined. The feasibility of using large panel processing equipment borrowed from the LCD industry for the processing of panel sizes up to 500 mm/spl times/500 mm is assessed in a preliminary study, and a cost model is presented. Results presented indicate that significant cost reductions can be obtained in going to LCD panel sizes for MCM-D processing provided volumes are in excess of 250 K 50 mm/spl times/50 mm substrate equivalents per year.<<ETX>>
electronic components and technology conference | 2009
Zhaozhi Li; Paul N. Houston; Daniel F. Baldwin; Eugene A. Stout; Theodore G. Tessier; John L. Evans
Market demand is increasing for even higher packaging densities, smaller size, lower cost, and more heterogeneous functionality. As a result, three dimensional (3D) packaging has emerged as a leading packaging solution. This paper introduces a 3D Wafer Level CSP packaging architecture that provides a cost effective, rapid time to market alternative to emerging 3D die to wafer integration technologies.
electronic components and technology conference | 1995
A.J.G. Strandjord; Philip Garrou; Robert Heistand; Theodore G. Tessier
This paper demonstrates how laminate based printed-wiring-board technology (PWB) and thin film deposited dielectric technology (MCM-D) can be combined to form a low-cost solution for microelectronic interconnect schemes which require high density circuitry. A multilayer telecommunications module was fabricated to demonstrate the feasibility of this MCM-LD concept. Standard copper-clad laminates were processed using conventional PWB techniques to form the first level of metal interconnects (75 /spl mu/m lines and spaces). A photosensitive benzocyclobutene layer was coated onto the boards and patterned to form 50 /spl mu/m/spl times/200 /spl mu/m nested vias down to the metal lines. A second metal interconnect layer was formed from a sputtered seed layer and plated up copper. Chip interconnection was carried out using gold wirebonding. Several large-area-processing (LAP) techniques were evaluated to determine the compatibility of the two interconnect technologies and to demonstrate the cost advantages of manufacturing large panels at high throughput levels. Spin coating, spray coating, meniscus coating, and extrusion coating were compared as dielectric deposition options and an in-line belt furnace was used to cure the dielectric layers on the laminate boards (rapid thermal curing). Laminate materials which were evaluated include: FR-4 (epoxy), BT (bismaleimide-triazine), PI (polyimide), and CE (cyanate ester). >
electronic components and technology conference | 1991
Theodore G. Tessier; William F. Hoffman; John W. Stafford
The use of reactive ion etching and excimer laser ablation processes for the etching of vias through thick layers of dielectric (up to 25 mu m thick) in multichip module fabrication is evaluated. A comparison of possible masking schemes is presented. Typical etch results obtained by these techniques are shown and compared. A throughput analysis of these two via fabrication techniques for use in a high-volume multichip module substrate facility is presented. Results obtained suggest that laser processing is a viable alternative to reactive ion etching for multichip module substrate via fabrication.<<ETX>>
Additional Conferences (Device Packaging, HiTEC, HiTEN, & CICMT) | 2015
Gene Stout; Doug Scott; Anthony Curtis; Guy F. Burgess; Theodore G. Tessier
The electroplating of underlying metal redistribution layers, under-bump metallization (UBM) layers, WLCSP, Cu pillar and other flip chip applications is well established in the semiconductor indus...
Archive | 1996
Theodore G. Tessier; Kenneth Kaskoun; David A. Jandzinski
Archive | 1996
Theodore G. Tessier; John W. Stafford; David A. Jandzinski
Archive | 1997
Melissa E. Grupen-Shemansky; Jong-Kai Lin; Theodore G. Tessier