Thiago Hanna Both

Voltage scaling and aging effects on soft error rate in SRAM-based FPGAs

This work investigates the effects of aging and voltage scaling in neutron-induced bit-flip in SRAM-based Field Programmable Gate Array (FPGA). Experimental results show that aging and voltage scaling can increase in at least two times the susceptibility of SRAM-based FPGAs to Soft Error Rate (SER). These results are innovative, because they combine three real effects that occur in programmable circuits operating at ground-level applications. In addition, a model at electrical level for aging, soft error and different voltages in SRAM memory cells was described to investigate by simulation in more details the effects observed at the practical neutron irradiation experiment. Results can guide designers to predict soft error effects during the lifetime of devices operating in different power supply mode.

Deterministic Methodology for Electrical Simulation of BTI Induced Pulse Broadening

This paper presents an analysis of the bias temperature instability (BTI) induced pulse broadening of single event transients (SETs) in inverter chains. A novel deterministic simulation methodology for BTI, using the trapping/de-trapping framework, is proposed and implemented in a commercial SPICE tool. The developed simulator properly predicts the possibility that an SET pulse may suffer propagation-induced pulse broadening (PIPB). The PIPB was analyzed in terms of supply voltage and input signal frequency. The simulations results are in agreement with experimental results from the literature.

Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs

This work investigates the effects of aging and voltage scaling in neutron-induced bit-flip in SRAM-based FPGAs. Experimental results show that aging and voltage scaling can increase in at least two times the susceptibility of SRAM-based FPGAs to Soft Error Rate (SER). These results are innovative, because they combine three real effects that occur in programmable circuits operating at ground-level applications. In addition, a model at electrical simulation for aging, soft error and different voltages was described to investigate the effects observed at the practical neutron irradiation experiment. Results can guide designers to predict soft error effects during the lifetime of devices operating in different power supply mode.

Modeling and simulation of the charge trapping component of BTI and RTS

Abstract Charge trapping phenomena is known to be a major reliability concern in modern MOSFETS, playing a significant role in aging through Bias Temperature Instability (BTI) and dominating low-frequency noise behavior. An electrical level modeling and simulation approach, valid at DC, AC and transient operation conditions is presented. Detailed statistical analysis is provided, aiming at proper modeling of BTI and noise variability, as well as to facilitate the understanding of physical mechanisms behind BTI and noise that are difficult to obtain otherwise. Case studies relevant for practical applications and understanding of the basic mechanisms are presented and critically discussed.

Measurements of radiation effects on a 4 Mb PSRAM memory

The results of a static test of total ionizing dose (TID) effects on an ISSI 4Mb PSRAM memory are reported in this work. The irradiation was performed at the IEAv’s Laboratory of Ionizing Radiation with 1.17 and 1.32 MeV gamma-rays from a 60Co source at a dose rate of 2.5 krad/h up to an accumulated dose of 215.7 krad. The TID threshold for bit flip found in this experiment was 52.5 krad. From a sampling of 4096 memory addresses it was estimated a bit flip rate of approximately 50% at an accumulated dose of 215.7 krad.

A PLL for clock generation with automatic frequency control under TID effects

This paper presents a PLL scheme for clock generation with a Total Ionizing Dose (TID) degradation detector. Externally to the PLL circuitry, when the degradation due to TID effects reaches a certain predefined threshold, the circuit reduces the clock frequency output. To compensate for the increased delay caused by the total dose effect (TID), the system increases the clock period in order to avoid timing violations, increasing the chip lifespan. The circuit was designed in a 0.35μm CMOS process and simulated with HSPICE tool.