Satwinder Malhi

Characteristics and three-dimensional integration of MOSFET's in small-grain LPCVD polycrystalline Silicon

Building on nearly two decades of reported results for MOSFETs fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFETs in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.

A trench transistor cross-point DRAM cell

A 1T DRAM cell with both the transistor and the capacitor fabricated on the sidewalls of a deep trench is described. Trench Transistor Cell (TTC) fabrication and characterization are discussed.

A 4-Mbit DRAM with trench-transistor cell

An experimental 5-V-only 1M-word/spl times/4-bit dynamic RAM with page and SCD modes has been built in a relatively conservative 1-/spl mu/m CMOS technology with double-level metal and deep trenches. It uses a cross-point one-transistor trench-transistor cell that measures only 9 /spl mu/m/SUP 2/. A double-ended adaptive folded bit-line architecture used on this DRAM provides the breakthrough needed to take full density advantage of this cross-point cell. The 30-fF storage capacitance of this cell is expected to provide high alpha immunity since the charge is stored in polysilicon and is oxide isolated from the substrate. A 150-ns now-address-stable access time and 40-ns column-address-strobe access time have been observed.

A 4Mb DRAM with cross point trench transistor cell

This report will describe the design of a 9.8mm×10.2mm 1MW×4b DRAM fabricated in a 1μm double-level metal CMOS technology featuring trench-transistor cells measuring 9μm2. Row and static column access times are 170ns and 30ns, respectively.

Hot-electron degradation of n-channel polysilicon MOSFETs

The stability of the hydrogen passivation in hydrogenated n-channel polysilicon MOSFETs has been studied under thermal stress and hot-electron stress at elevated temperatures. Although the hydrogen passivation is stable at 150 degrees C, channel hot-electron stress at high temperatures appears to create additional grain boundary traps, presumably by breaking the Si-H bonds at the grain boundaries. This mechanism is in addition to the creation of acceptor-type fast interface states that occur in bulk MOSFETs. >

Characteristics and Three-Dimensional Integration of MOSFET's in Small-Grain LPCVD Polycrystalline Silicon

Building on nearly two decades of reported results for MOSFETs fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFETs in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.

Novel SOI CMOS design using ultra thin near intrinsic substrate

A novel SOI CMOS design has been explored. It utilizes an ultra thin near intrinsic substrate wherein no channel doping is introduced during processing. The enhancement operation is realized solely by proper adjustment of work function difference through p+ poly gate for n-channel devices and n+ poly gate for p-channel devices. The absence of depletion charge in this structure is conducive to improved drive current and threshold control. The structure has been realized by implanted buried oxide SOI technology.

Stacked CMOS SRAM cell

A static random access memory (SRAM) cell with cross-coupled stacked CMOS inverters is demonstrated for the first time. In this approach, CMOS inverters are fabricated with a laser recrystallized p-channel device stacked on top of and sharing the gate with a bulk n-channel device using a modified two-polysilicon n-MOS process. The memory cell has been exercised through the write and read cycles with external signal generators while the output is buffered by an on-chip, stacked-CMOS-inverter-based amplifier.

The Top Silicon Layer of SOI Formed by Oxygen Ion Implantation

High dose oxygen ion implantation has been used to form a buried oxide layer in Czochralski grown silicon. Wafers were implanted with 300 keV O2+ to a total dose of 1.32 × 1018 ions cm-2. A 0.5 m thick SiO2 layer is formed beneath a 0.17 ¿m thick top Si layer. Epitaxial films were grown on both annealed and unannealed wafers. Samples were subsequently annealed at 1150°C for times from 10 to 240 minutes in either Ar or N2. The highest quality epitaxial layers were obtained with substrates that were annealed after implantation, but prior to epitaxial growth for 2 hrs at 1150°C followed by 4 hrs at 1150°C after epitaxial growth. RBS channeling shows that the top 300 nm of these films have <110> channel backscattering yields lower than any SOI produced to date. The buried oxide plus epitaxial process is a leading candidate for VLSI applications.

p-Channel MOSFET's in LPCVD PolySilicon

p-channel MOSFETs have been fabricated in LPCVD polysilicon. A 5000-Å n+poly acts as the gate electrode on which a 500-Å thermal oxide is grown to act as the gate insulator. Then a 1500-Å LPCVD polysilicon layer is deposited at 620°C and is subsequently boron doped to form the conductive channel. Devices with channel length as small as 2 µm show well-behaved transistor characteristics. The drive current and leakage current are as suitable for usage as load element in memory applications. At large gate voltages the accumulation hole mobility is 9 cm2/V.s. The drain-to-source breakdown voltage exceeds -20 V.