Thomas A. Phillips

CHARACTERIZING AN ANALOG AMPLIFIER UTILIZING A FERROELECTRIC TRANSISTOR

ABSTRACT The use of ferroelectric materials for digital memory devices is widely researched and implemented, but ferroelectric devices also posses unique characteristics that made them have interesting and useful properties in analog circuits. Because ferroelectric transistors posses the properties of hysteresis and nonlinearity, an analog amplifier containing an FeFET has very different characteristics than one with a traditional FET. This paper characterizes the properties of a simple analog amplifier using both a traditional FET and a ferroelectric FET. The characterization includes voltage transfer, gain, frequency response, and operating modes. Because of the hysteresis effects the FeFET amplifier has two distinct operating modes, each with significantly different properties. These two regions have very different gain characteristics and are nonlinear. This has the effect of being able to program the FeFET to have two different voltage transfer/current characteristics with a single device. This can allow a flexible circuit that can change its analog properties on-the-fly with only a programming pulse. Modeled and measured data are presented showing the characteristics of this device. Comparisons are made between the ferroelectric device and the properties of a standard analog amplifier. Potential benefits and possible uses of such a device are presented.

MODELING OF A FERROELECTRIC FIELD-EFFECT TRANSISTOR STATIC RANDOM ACCESS MEMORY CELL

ABSTRACT Ferroelectric devices provide many benefits over standard Metal-Oxide Semiconductor (MOS) devices. There is considerable interest in the aerospace industry in the reliability and radiation hardening effects that the ferroelectric memory devices provide. The modeling of a Ferroelectric Static Random Access Memory (FeSRAM) cell is to be investigated. The SRAM memory cell under investigation is a standard four transistor cell with the MOS Field-Effect Transistors (MOSFETs) replaced with Ferroelectric Field Effect Transistors (FeFETs). The SRAM FeFETs were simulated by using a previously developed model. Comparisons were made between the FeSRAM and a standard MOSFET SRAM.

METAL-FERROELECTRIC-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR NAND GATE SWITCHING TIME ANALYSIS

ABSTRACT Previous research investigated the modeling of a NAND gate constructed of n-channel Metal-Ferroelectric-Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate.

Modeling of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate

The modeling of a NAND gate constructed of Metal-Ferroelectric-Semiconductor Field Effect Transistors (MFSFETs) has been investigated. Initially, an inverter circuit was modeled using a n-channel MFSFET with positive polarization for a standard CMOS inverter n-channel transistor and a n-channel MFSFET with negative polarization for the standard CMOS inverter p-channel transistor. The MFSFETs were simulated by using a previously developed MFSFET model which utilized a partitioned ferroelectric layer. Then a 2-input NAND gate was modeled similar to the inverter gate. The data shows that it is feasible to construct a NAND gate with MFSFET transistors.

Sonos Nonvolatile Memory Cell Programming Characteristics

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory is gaining favor over conventional EEPROM FLASH memory technology. This paper characterizes the SONOS write operation using a nonquasi-static MOSFET model. This includes floating gate charge and voltage characteristics as well as tunneling current, voltage threshold and drain current characterization.

Characteristics Of Ferroelectric Logic Gates Using a Spice-Based Model

A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates.

A Novel Metal-Ferroelectric-Semiconductor Field-Effect Transistor Memory Cell Design

The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated. A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the “1” and “0” logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the “1” and “0” logic states for a long period of time.

Modeling of Sonos Memory Cell Erase Cycle

This paper investigates the Silicon-oxide-nitride-oxide-silicon (SONOS) memory cell erase cycle. A nonquasi-static (NQS) MOSFET model was developed and implemented in software. The model equations were incrementally solved at each time step. During an erase cycle, a negative pulse is applied to the gate which causes Fowler-Nordheim tunneling between the floating gate and channel. The SONOS floating gate voltage, tunneling current, and threshold voltage were characterized during this erase cycle. Comparisons were made between the model predictions and experimental data for the threshold voltage.

PERFORMANCE MEASUREMENT OF A MULTI-LEVEL/ANALOG FERROELECTRIC MEMORY DEVICE DESIGN

ABSTRACT Increasing the memory density and utilizing the unique characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes the characterization of a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. This paper presents measurements of an actual prototype memory cell. This prototype is not a complete implementation of a device, but instead, a prototype of the storage and retrieval portion of an actual device. The performance of this prototype is presented with the projected performance of the overall device. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.