Fat D. Ho

A comprehensive analytical model for metal-insulator-semiconductor (MIS) devices

A comprehensive model for metal-insulator-semiconductor (MIS) devices under dark conditions which consists of a wide range of parameters has been developed. Parameters neglected by other authors have been included. The effects of surface states, silicon dioxide thickness, substrate doping, fixed oxide charges, substrate thickness, and metal work function are taken into account. The permittivity and barrier height of thin oxide are included in the calculation. The limits on equilibrium and nonequilibrium are explored. >

A comprehensive analytical model for metal-insulator-semiconductor (MIS) devices: a solar cell application

As an application of the authors previous model for MIS (metal-insulator-semiconductor) devices, a detailed model for MIS solar cells has been developed that covers a wide range of parameters, including surface states, silicon dioxide thickness, substrate doping, fixed oxide charges, substrate thickness, and metal work function. It also takes the nonequilibrium conditions into consideration. The effects of using the actual permittivity and barrier height of thin oxide are discussed. >

Modeling of Metal-Ferroelectric-Semiconductor Field Effect Transistors

Abstract The characteristics for a MFSFET (metal-ferroelectric-semiconductor field effect transistor) is very different than a conventional MOSFET and must be modeled differently. The drain current has a hysteresis shape with respect to the gate voltage. The position along the hysteresis curve is dependent on the last positive or negative polling of the ferroelectric material. The drain current also has a logarithmic decay after the last polling. A model has been developed to describe the MFSFET drain current for both gate voltage on and gate voltage off conditions. This model takes into account the hysteresis nature of the MFSFET and the time dependent decay. The model is based on the shape of the Fermi-Dirac function which has been modified to describe the MFSFETs drain current. This is different from the model proposed by Chen et. al.[1] and that by Wu[2].

A numerical model for MOSFET's from liquid-nitrogen temperature to room temperature

A two-dimensional Gummel model is developed to simulate the electrical behavior of silicon MOSFETs in the temperature range of 77 to 300 degrees Kelvin. In this paper, first a short description of the simulator is presented. Then, we study differences between the results when Fermi-Dirac distribution is used and when Boltzmann distribution is used for mobile carriers in calculating the ionized dopant concentrations and the current densities for moderately doped n- and p-channel enhancement-mode MOSFETs. We also investigate the differences between the results when the two different distribution functions are used for mobile carriers in calculating the ionized impurities at high channel concentration and the current densities for moderately doped n-channel depletion-mode MOSFETs. There are no differences for drain currents using these two different statistics. Moreover, using Boltzmann statistics, reduces the computational effort by 40 to 50 percent in this model. In addition, we evaluate the boundary conditions using these two different distribution functions. The differences between the obtained currents in linear and saturation regions for an n-channel enhancement mode MOSFET is less than 8 percent. Some I-V results attained from the simulation of buried-channel NMOS transistors are presented and compared with the experimental data in the literature. The model is also checked for comparison with some experimental data reported in the literature for a PMOS, an NMOS, and a CMOS inverter specially designed for low temperature operation. In addition, the I-V characteristics obtained by our calculations are compared with those of Selberherrs to check for the validity and accuracy of the simulator. Reasonable agreement between the simulated and experimental data is obtained. >

SPICE modeling of cascade solar cells

An equivalent circuit representing a two-junction cascade solar cell is presented. The solar cell diode equations are applied. Terms for the light-generated currents, diffusion currents, space charge recombination currents, series and shunt resistance, the resistance for the window layer and the substrate, and the equivalent resistance for the tunnel diode are included. An AlGaAs/GaAs cascade solar cell is considered as an example. SPICE was used to simulate the cascade solar cell for the following: the cascade solar cell I-V curve with temperature as a parameter, the cascade cell P-V curves with temperature as a parameter, open-circuit voltage of the cascade cell versus temperature, and fill factor of the cascade cell versus temperature. The results of this SPICE simulation compared favorably with the data available in the published literature.<<ETX>>

CHARACTERIZING AN ANALOG AMPLIFIER UTILIZING A FERROELECTRIC TRANSISTOR

ABSTRACT The use of ferroelectric materials for digital memory devices is widely researched and implemented, but ferroelectric devices also posses unique characteristics that made them have interesting and useful properties in analog circuits. Because ferroelectric transistors posses the properties of hysteresis and nonlinearity, an analog amplifier containing an FeFET has very different characteristics than one with a traditional FET. This paper characterizes the properties of a simple analog amplifier using both a traditional FET and a ferroelectric FET. The characterization includes voltage transfer, gain, frequency response, and operating modes. Because of the hysteresis effects the FeFET amplifier has two distinct operating modes, each with significantly different properties. These two regions have very different gain characteristics and are nonlinear. This has the effect of being able to program the FeFET to have two different voltage transfer/current characteristics with a single device. This can allow a flexible circuit that can change its analog properties on-the-fly with only a programming pulse. Modeled and measured data are presented showing the characteristics of this device. Comparisons are made between the ferroelectric device and the properties of a standard analog amplifier. Potential benefits and possible uses of such a device are presented.

Transient Simulation to Analyze Flash Memory Erase Improvements Due to Germanium Content in the Substrate

We present a detailed and accurate physics-based transient simulation for modeling Flash memory erase characteristics when the substrate contains different percentages of germanium (Ge). Typical cells are erased by moving electrons from the floating gate to the drain, source, or substrate. This paper addresses substrate erase modeling using a simulation based on the solution to Poissons equation with Ge percentage as an independent variable. The goal of this paper is to demonstrate the derivation of an accurate erase simulation and show the improvements that can be achieved by using silicon-germanium (SiGe) substrate material versus silicon (Si) only. Several papers have been published on MOSFETs with SiGe substrates, but none has been published on the use of SiGe substrates in Flash memory.

Satellite test of radiation impact on Ramtron 512K FRAM

The Memory Test Experiment is a space test of a ferroelectric memory device on a low Earth orbit satellite. The test consists of writing and reading data with a ferroelectric based memory device. Any errors are detected and are stored on board the satellite. The data is send to the ground through telemetry once a day. Analysis of the data can determine the kind of error that was found and will lead to a better understanding of the effects of space radiation on memory systems. The test will be one of the first flight demonstrations of ferroelectric memory in a near polar orbit which allows testing in a varied radiation environment. The memory devices being tested is a Ramtron Inc. 512K memory device. This paper details the goals and purpose of this experiment as well as the development process. The process for analyzing the data to gain the maximum understanding of the performance of the ferroelectric memory device is detailed.

Metal-Ferroelectric-Semiconductor Field-Effect Transistor Modeling Using a Partitioned Ferroelectric Layer

A combination empirical/theoretical n-channel metal-ferroelectric-semiconductor field-effect transistor (MFSFET) model is developed. The model is based on a partition concept where the MFSFET ferroelectric material is segmented, allowing each individual segment to maintain an independent polarization solution as a function of applied electric field history. Modifications are made to pertinent classical metal-oxide-semiconductor field-effect transistor device equations to include the presence of ferroelectric dipole polarization charge. The models usage of ferroelectric polarization is numerical in nature, allowing both analytic and non-analytic ferroelectric polarization models to be used. Simulation results showing the effects of the ferroelectric model parameters on MFSFET drain current are presented, including active and remnant saturated hysteresis and retention.

Characterization of a Common-Source Amplifier Using Ferroelectric Transistors

This paper presents empirical data that was collected through experiments using a FeFET in the established common-source amplifier circuit. The unique behavior of the FeFET lends itself to interesting and useful operation in this widely used common-source amplifier. The paper examines the effect of using a ferroelectric transistor for the amplifier. It also examines the effects of varying load resistance, biasing, and input voltages on the output signal and gives several examples of the output of the amplifier for a given input. The difference between a common-source amplifier using a ferroelectric transistor and that using a MOSFET is addressed.