Thomas D. Bonifield

Nanophotonic integration in state-of-the-art CMOS foundries

We demonstrate a monolithic photonic integration platform that leverages the existing state-of-the-art CMOS foundry infrastructure. In our approach, proven XeF2 post-processing technology and compliance with electronic foundry process flows eliminate the need for specialized substrates or wafer bonding. This approach enables intimate integration of large numbers of nanophotonic devices alongside high-density, high-performance transistors at low initial and incremental cost. We demonstrate this platform by presenting grating-coupled, microring-resonator filter banks fabricated in an unmodified 28 nm bulk-CMOS process by sharing a mask set with standard electronic projects. The lithographic fidelity of this process enables the high-throughput fabrication of second-order, wavelength-division-multiplexing (WDM) filter banks that achieve low insertion loss without post-fabrication trimming.

Demonstration of an electronic photonic integrated circuit in a commercial scaled bulk CMOS process

We demonstrate the first photonic chip designed in a commercial bulk CMOS process (65 nm node) using standard process layers combined with scalable post-processing, enabling dense photonic integration with high-performance microprocessor electronics.

Failure Mode Detection and Process Optimization for 65 nm CMOS Technology

Short loop test flows have been commonly used in back end of line (BEOL) interconnect process development to speed up learning rates and improve yields. This paper presents case studies on the expanded use of short loop test chips to the shallow trench isolation (STI), gate and pre- metal dielectric (PMD)Z contact loops of a 65 nm process technology in addition to the BEOL. These test chips have been used to quickly identify and eliminate random and systematic defect mechanisms and generate a robust process flow, thus accelerating the rate of yield learning.