Byron Williams

RF CMOS on high-resistivity substrates for system-on-chip applications

The use of a high-resistivity substrate extends the capability of standard digital CMOS technology to enable the integration of high-performance RF passive components. The impact of substrate resistivity on the key components of RF CMOS for system-on-chip (SoC) applications is discussed. The comparison includes the transistor, transmission line, inductor, capacitor and varactor, as well as the noise isolation. We also discuss the integration issues including latch-up and well-well isolation in a 0.35-/spl mu/m Cu metal pitch, 0.1-/spl mu/m-gate-length RF CMOS technology.

0.1 /spl mu/m RFCMOS on high resistivity substrates for system on chip (SOC) applications

This paper describes the impact of substrate resistivity on the key components of the radio frequency (RF) CMOS for the system on chip (SOC) applications. The comparison includes the transistor, inductor, capacitor, noise isolation, latch-up as well as the well-to-well isolation in a 0.1 /spl mu/m (physical gate length) CMOS technology.

A 65 nm CMOS technology for mobile and digital signal processing applications

This paper presents a 65 nm CMOS technology that achieves a logic density of 900 k-gates/mm/sup 2/ and a SRAM memory density of 1.4 Mb/mm/sup 2/ using a sub-0.49 /spl mu/m/sup 2/ bitcell. Key features of a low cost technology option for mobile products (MP) and a high performance technology option (HP) for DSP based applications are described.

Solution-derived electrodes and dielectrics for low-cost and high-capacitance trench and Through-Silicon-Via (TSV) capacitors

This paper explores and demonstrates a novel technique to conformally coat solution-derived electrodes and dielectric films over Through-Silicon-Via (TSV) or Through-Silicon Trench (TST) structures. In this technique, precursor solution for electrode or dielectric coatings is dispensed on the top of a TSV wafer and infiltrated through the via by creating a pressure gradient. Two material systems used in capacitors, Lanthanum Nickel Oxide (LNO) as electrode and Lead Zirconate Titanate (PZT) as dielectric, were deposited on the TSV surfaces using this technique. SEM cross-section analysis showed that the vacuum-infiltration can be extended to conformally coat on trenches with aspect ratios of greater than 5. A planar capacitor with density of 3 μF/cm2 and low leakage was fabricated to demonstrate the material compatibility. Using this technique, a trench capacitor device can be fabricated with an all-solution coating process, without involving any expensive deposition tools. This can thus eliminate costly platinum electrodes that are frequently required to yield high permittivity PZT films. This technique can also address the through-put limitations of todays conformal deposition technologies such as sputtering, Chemical Vapor Deposition (CVD) and Atomic Layer Deposition (ALD). The tool and process can also be applied to other 3D silicon structures where conformal ceramic coatings are needed.

All-Solution Thin-film Capacitors and Their Deposition in Trench and Through-Via Structures

Thin integrated passive devices (IPDs) will play a critical role in the miniaturization of future high-performance electronic and bioelectronic systems. Silicon-based capacitors are currently manufactured with expensive processes such as sputtering and atomic layer deposition. Solution-deposited electrodes and dielectrics in trench and through-via structures provide alternative low-cost routes. Two solution-deposition techniques, spin-coating and vacuum infiltration, are investigated in this paper. A representative all-solution-derived thin-film capacitor consisting of sol-gel lanthanum nickel oxide (LNO) as the electrode, and sol-gel lead zirconate titanate as the dielectric thin-film is demonstrated in the first part of this paper. The role of barriers in reducing leakage currents is studied using three electrode systems: LNO/Si, LNO/ZrO2/Si, and LNO/Pt/Ta/Si. Capacitors with LNO electrodes directly deposited on naturally oxidized silicon resulted in higher leakages, more defects and a lower yield. The results show that the zirconia barrier suppresses the leakage current in the dielectric. The second part of this paper describes sol-gel films deposited in the through-via and trench surfaces to demonstrate the sol-gel conformal coating technique. Scanning electron microscopy cross-section analysis shows that the vacuum infiltration conformally coated through-vias. These solution deposition techniques may have the potential to fabricate IPD capacitors at low cost.