Thomas L. Turflinger

Single event transient pulse widths in digital microcircuits

The radiation effects community has long known that single event transients in digital microcircuits will have an increasing importance on error rates as device sizes shrink. However separating these errors from static errors in latch cells has often proved difficult. Thus determining both the significance and the nature of these transient errors has not been easy. In this study, by utilizing a latch that is radiation hard at static clock frequencies the errors due to transients could be separated. By separating the transient error rate from the static upset error rate, the pulse structure of the propagating transients was studied using SPICE. The implications of these pulsewidths will also be discussed.

Single event transient pulsewidth measurements using a variable temporal latch technique

A new test structure was designed for measuring the pulsewidths of transients created by SETs. Experimental data was gathered using heavy ions from LETs of 11.5 to 84MeV-cm/sup 2//mg. The pulsewidths of SETs generated using heavy ions are measured using a variable temporal latch. Our SETs widths at low LETs agree exceptionally well with previous localized beam measurements.

Digital Single Event Transient Trends With Technology Node Scaling

We have measured the single-event-transient (SET) width as a function of cross-section over three CMOS bulk/epitaxial technology nodes (0.25, 0.18 and 0.13 mum) using an identically scaled programmable-delay temporal-latch technique. Both the maximum width of the SET pulse and the cross-section are shown to depend primarily on the supply voltage, with a substantial increase in transient width and cross-section with lower operating potentials

Variation of digital SET pulse widths and the implications for single event hardening of advanced CMOS processes

Single event transient (SET) pulse widths produced from heavy ion irradiation in digital ICs are measured using a variable-delay temporal-latch test structure. We show for the first time that there is a wide distribution of SET pulse widths created by heavy ion radiation in digital CMOS logic at given linear energy transfer (LET) levels. We were able to measure SET pulse widths from as short as 344 ps to greater than 1.5 ns in 0.18 /spl mu/m CMOS technology at LETs greater than 80 MeV-cm /sup 2//mg. Depending on LET, the cross section of the very long SET pulses were as much as four orders of magnitude smaller than for the shorter pulse widths. This has substantial implications for hardening techniques; specifically, we now know that we can dramatically improve the SET hardness without suffering the speed penalties required to remove the longest transients.

Evaluation of proposed hardness assurance method for bipolar linear circuits with enhanced low dose rate sensitivity (ELDRS)

Data are presented on several low dose rate sensitive bipolar linear circuits to evaluate a proposed hardness assurance method. The circuits include primarily operational amplifiers and voltage comparators with a variety of sensitive components and failure modes. The proposed method, presented in 1997, includes an option between a low dose rate test at 10 mrd(Si)/s and room temperature and a 100/spl deg/C elevated temperature irradiation test at a moderate dose rate. The results of this evaluation demonstrate that a 10 mrd(Si)is test is able (in ail but one case) to bound the worst case response within a factor of 2. For the moderate dose rate, 100/spl deg/C test the worst case response is within a factor of 3 for 8 of 11 circuits, and for some circuits overpredicts the low dose rate response. The irradiation bias used for these tests often represents a more degrading bias condition than would be encountered in a typical space system application.

Current single event effects and radiation damage results for candidate spacecraft electronics

We present data on the vulnerability of a variety of candidate spacecraft electronics to proton and heavy ion induced single event effects, proton-induced damage, and total ionizing dose. Devices tested include optoelectronics, digital, analog, linear bipolar, hybrid devices, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and DC-DC converters, among others.

An updated data compendium of enhanced low dose rate sensitive (ELDRS) bipolar linear circuits

The 1996 total dose data compendium on ELDRS in bipolar linear circuits is updated. The new data include 37 data sets at high and low dose rate on 29 part types from nine manufacturers. A new table on elevated temperature irradiation has been added. References for each data set are provided.

Digital Device Error Rate Trends in Advanced CMOS Technologies

In this paper, data are presented from test chips in four technology nodes. With this data, the trends in single event effects as feature sizes shrink are studied. Some of the trends discussed include upset thresholds, shrinking cross sections, multiple bit upsets, and per bit error rate trends. Also included in this paper is some of the first ever heavy ion data from a 65 nm CMOS technology. With data from the 250 nm, 180 nm, 90 nm, and 65 nm technology nodes, the past, present, and future of what the radiation effects community has dealt with and will be dealing with when it comes to single event effects is presented

Enhanced low dose rate sensitivity (ELDRS) of linear circuits in a space environment

To investigate the ELDRS effect in a real space environment, an experiment was designed, launched, and placed in a highly elliptical orbit in November 1997. After its deployment, the electrical responses of several bipolar transistors and linear circuits have been and continue to be recorded once during every 12-hour orbit. System dosimeters are monitored to establish an average accumulated dose per orbit. With this information, the electrical parameter data are correlated with the dosimetry data to determine the total dose response of each device. This paper updates information on the ELDRS experiment through May 14, 1999. As of this date, the experiment has been in flight for a period of 18 months and has accumulated an approximate dose of 18 krd(Si). For comparison, devices, specifically linear circuits with the same date code, were irradiated using Co-60 sources, herein defined as ground-based tests. The ground-based tests are used to evaluate two hardness assurance tests, a room temperature irradiation at 10 mrd(Si)/s and an elevated temperature irradiation at 100/spl deg/C and 10 rd(Si)/s and to evaluate the ELDRS response. To that end, irradiations were performed at room temperature, approximately 22/spl deg/C, at fixed dose rates of 100, 1, and 0.01 rd(Si)/s and at elevated temperature, approximately 100/spl deg/C, at a fixed dose rate of 10 rd(Si)/s. Currently, irradiations are being performed at room temperature at a fixed dose rate of 0.001 rd(Si)/s. Comparing the ground-based data to the flight data clearly demonstrates that enhanced parametric degradation has occurred in the flight parts. The two hardness assurance screens predicted ELDRS but the design margin for the elevated temperature test may not be adequate.

Comparison of heavy ion and proton induced combinatorial and sequential logic error rates in a deep submicron process

Digital single event transients induced in combinatorial logic are quickly becoming a significant error source as circuit feature sizes shrink and digital circuits operate faster. In this paper, we are able to compare the combinatorial logic error rate to the sequential logic error rate in both heavy ion and proton environments in a simple digital circuit created in a 0.18 /spl mu/m CMOS technology. We are able to do this by comparing data from two unique test chips.