Thomas Pompl

Reliability aspects of gate oxide under ESD pulse stress

Power law time-to-breakdown voltage acceleration is investigated down to ultra-thin oxides (1.1 nm) in the ESD regime in inversion and accumulation. Breakdown modes, oxide degradation and device drifts under ESD like stress are discussed as function of the oxide thickness. The consequent impacts on the ESD design window are presented.

Investigation of ultra-thin gate oxide reliability behavior by separate characterization of soft breakdown and hard breakdown

It is shown in this work that the soft breakdown can follow a significantly different temperature and field acceleration behavior than the dielectric breakdown (hard breakdown). These properties have a strong influence on reliability prediction of ultra-thin oxides and can result in misinterpretation if soft breakdown and hard breakdown events are mixed up during gate oxide reliability testing. The activation energy and the field acceleration of the soft breakdown are compared to the disturbed-bond breakage process proposed in the thermochemical E-model. It is concluded that soft breakdown can be caused by H-Si and H-O bond breakage due to the electric field in the oxide. The activation energy for soft breakdown also indicates that formation of a soft breakdown path is influenced by hydrogen diffusion in the oxide.

Influence of gate oxide breakdown on MOSFET device operation

Abstract The degradation of MOS transistor operation due to soft breakdown and thermal breakdown of the gate oxide was studied. Important transistor parameters were monitored during homogeneous stress at elevated temperature until a breakdown event occurred. In case of NMOSFETs the only noticeable signature of soft breakdown is an increase in off current due to enhanced gate induced drain leakage current (GIDL). A model is proposed and it is concluded that this effect only arises if the soft breakdown is located within the gate-to-drain overlap region. The influence of soft breakdown on PMOSFETs is discussed based on the model of enhanced GIDL for NMOSFETs. The degradation due to thermal breakdown of the gate oxide was investigated in detail. As a conclusion, a careful selection of device parameters is necessary in order to detect a device breakdown caused by thermal gate oxide breakdown.

Lifetime Prediction for CMOS Devices with Ultra Thin Gate Oxides Based on Progressive Breakdown

Progressive breakdown observed in CMOS devices with ultra thin gate oxides can significantly increase the time dependent dielectric breakdown (TDDB) reliability margin of digital CMOS products. The voltage acceleration, the failure distribution of the progressive breakdown and the methodology for quantification of the progressive breakdown is discussed. Extensive experimental data are provided, enabling its implementation

Voltage acceleration of time-dependent breakdown of ultra-thin gate dielectrics

Experimental results support the power-law model to correctly describe the voltage acceleration of time-dependent dielectric breakdown (TDDB) in an oxide thickness range where direct tunnelling of electrons is the primary leakage mechanism. The accessible experimental time range to prove a certain voltage acceleration behaviour is compared to the time range that needs to be covered during a projection to use conditions. Further, the problem of correct gate oxide breakdown detection in PFET devices is discussed, because it strongly affects the determination of time to breakdown, Weibull slope, acceleration model, and acceleration factor.

Soft breakdown and hard breakdown in ultra-thin oxides

Abstract Soft breakdown (SBD) and hard breakdown (HBD) events are characterised separate of each other for a 3.4 nm gate oxide. It is shown that both breakdown events can have significantly different voltage and temperature acceleration behaviour. Further it is demonstrated by photoemission microscopy (PEM) for a 2.2 nm oxide that different types of breakdown paths exist. HBD-like and SBD-like breakdowns are found on the same gate area during constant voltage stress. PEM also points out that a structural change of a breakdown path can occur, usually referred to as thermal breakdown of SiO2. It is concluded that a separate characterisation of SBD and HBD events is correct, if the stress conditions do not cause this structural change for the first SBD event.

Gate voltage and oxide thickness dependence of progressive wear-out of ultra-thin gate oxides

The progressive wear-out of a breakdown path in ultra-thin gate oxides depends on oxide thickness and follows the intrinsic voltage acceleration model of time to breakdown. The quantification of progressive wear-out in this work is the critical step towards product relevant assessment of ultra-thin gate oxides.

Failure distributions of successive dielectric breakdown events

Experimental time-dependent dielectric breakdown (TDDB) distributions of standard CMOS hardware are used to demonstrate the problem of detecting a range of successive breakdown events, e.g., from the 5th to the 20th. Specifically, the range and the statistical distribution of successive breakdown events significantly change the shape of the cumulative failure distribution, which is crucial for the low percentile extrapolation. The observed behavior affects the correlation of integrated circuit failure distributions to dielectric breakdown as it is expected that circuit malfunction is caused by a range of successive breakdown events.

Modeling of substrate related extrinsic oxide failure distributions

The extrinsic oxide failure distributions of 6.8 nm thermal oxide on Czochralski (CZ) silicon wafers was investigated in detail. Using superposition of intrinsic Weibull distributions folded with a normal distribution of oxide thinning in COPs, enables one to describe the cumulative failure distributions of splits with different hydrogen pre-anneals. Voltage acceleration of individual Weibull distributions allows one to model experimental data of wafer level step stress and long term package level tests. The features of the linear E-model, 1/E-model and power law model are discussed in terms of thickness dependence of voltage acceleration. The results indicate that substrate related defects cause extrinsic oxide breakdown only at the late stage of device operation, even if the conservative linear E-model is assumed.

Contribution of interface traps to valence band electron tunneling in PMOS devices

The I-V characteristic of the negatively biased p-poly PMOS changes from near valence band electron injection to near conduction band electron injection. The Fermi level is the reference energy level for valence band electron tunneling rather than the valence band edge, which results in a voltage dependent barrier height. The proposed Interface State Injection Model explains this by electron injection from interface states, quickly recharged by band to trap tunneling due to the small depletion layer width in highly doped gate material.