Thomas Rinderknecht

High-frequency, at-speed scan testing

The authors describe new strategies where at-speed scan tests can be applied with internal PLL. They present techniques for optimizing ATPG across multiple clock domains and methodologies to combine both stuck-at-fault and delay-test vectors into an effective test suite.

Signature Based Diagnosis for Logic BIST

This paper presents a new approach for performing logic BIST diagnosis exclusively using MISR signatures. Unlike conventional logic BIST diagnosis approaches which require either huge test time or complicated logic BIST design and ATE flow, signature based diagnosis does not require dynamically changing MISR operations for each failing device. Our experimental data shows that signature based diagnosis can achieve similar diagnosis resolution with manageable diagnosis run time while eliminating most of the complexity associated with the traditional approach to logic BIST diagnostics.

Logic BIST with scan chain segmentation

This work presents a novel BIST (built-in self test) scheme with scan chain segmentation. In the scheme, a combination of pseudo random patterns and single-weight patterns have been applied to CUT (circuit under test). Scan chain is partitioned into multiple segments delimited by inverters. When a single weighted pattern is applied to a segmented scan chain, successive segments receive bit patterns with complementary weights. Several segment configurations may be required to achieve full fault coverage. In this scheme the control logic is inside the scan path and built-in self test can be implemented without compromising timing performance of CUT. Experiments show that our scheme can obtain very good fault coverage. Hardware implementation is simple and straightforward.

Hardware efficient LBIST with complementary weights

In this paper, a novel logic BIST (built-in self test) scheme with complementary weights is proposed. The BIST implementation combines random patterns with complementary-weight weighted patterns. A heuristic algorithm based on deterministic test set is developed to compute weight set with complementary weights. Hardware similar to bit-flipping is used to produce complementary weights. For random resistant ISCAS circuits, complete fault coverage can be achieved with very low hardware overhead. Experiments show that two complementary weights are sufficient for weighted random pattern testing and it presents a novel direction for exploiting weighted patterns.

On the Generation of Compact Deterministic Test Sets for BIST Ready Designs

In this work we consider ATPG methods tailored to BIST ready designs to improve compression of external tests for such designs. Proposed ATPG reduces external test set sizes and test data volumes by 24% in comparison to that obtained by a state of the art commercial ATPG for BIST ready designs.

ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction

As digital circuits grow in gate count so does the data volume required for manufacturing test. To address this problem several test compression techniques have been developed. This paper presents a novel and scalable technique for inserting observation points to aid compression by reducing pattern count and data volume. Experimental results presented for industrial circuits demonstrate the effectiveness of the method.

Logic BIST using constrained scan cells

This paper presents a novel scan cell based control point insertion technique which eliminates timing degradation of conventional control points in built-in self test (BIST) applications. In this approach, control points are encoded into scan chains. Observation points are applied to enhance fault coverage. At each phase, a set of control points are activated to detect a set of target faults. Compared to conventional test point insertion, scan cell based control points improve controllability of the core logic without compromising timing performance of circuit under test (CUT). Experimental results show that close to stuck-at fault coverage by automatic test pattern generation (ATPG) can be achieved by our BIST method.

Programmable Scan-Based Logic Built-In Self Test

This paper presents a programmable approach for performing scan-based logic built-in self test. This approach combines the techniques of reseeding and weighted random patterns testing. Reseeding is used to encode the bias cube and weighted patterns are used to fine tune the weight set. Experimental results show fault coverage comparable to ATPG can be achieved. Most importantly, the scheme fits well in the system test environment and high fault coverage can be obtained with a small number of reconfigurations on the BIST controller.