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Tin-Hao Kuo

TSMC

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Publication

Featured researches published by Tin-Hao Kuo.

Archive | 2012

Methods and Apparatus for Package on Package Devices with Reversed Stud Bump Through Via Interconnections

Yen-Chang Hu; Ching-Wen Hsiao; Chih-Hua Chen; Chen-Shien Chen; Tin-Hao Kuo

Archive | 2010

CENTRIPETAL LAYOUT FOR LOW STRESS CHIP PACKAGE

Chen-Hua Yu; Hao-Yi Tsai; Jiun Yi Wu; Tin-Hao Kuo

Archive | 2014

Pillar Structure having a Non-Planar Surface for Semiconductor Devices

Tin-Hao Kuo; Chen-Shien Chen; Ching-Wen Hsiao

Archive | 2012

Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices

Yu-Jen Tseng; Yen-Liang Lin; Tin-Hao Kuo; Chen-Shien Chen; Mirng-Ji Lii

Archive | 2016

Dummy flip chip bumps for reducing stress

Sheng-Yu Wu; Tin-Hao Kuo; Chita Chuang; Chen-Shien Chen

Archive | 2011

Connecting Function Chips To A Package To Form Package-On-Package

Pei-Chun Tsai; Sheng-Yu Wu; Ching-Wen Hsiao; Tin-Hao Kuo; Chen-Shien Chen; Chung-Shi Liu; Chien-Hsiun Lee; Mirng-Ji Lii

Archive | 2012

Substrate Stand-Offs for Semiconductor Devices

Cheng Hung Shen; Tin-Hao Kuo; Chen-Cheng Kuo; Chen-Shien Chen; Yao-Chun Chuang

Archive | 2012

Conical-shaped or tier-shaped pillar connections

Tin-Hao Kuo; Chen-Shien Chen; Mirng-Ji Lii; Chen-Hua Yu; Sheng-Yu Wu; Yao-Chun Chuang

Archive | 2012

Bump Structure and Method of Forming Same

Guan-Yu Chen; Yu-Wei Lin; Yu-Jen Tseng; Tin-Hao Kuo; Chen-Shien Chen

Archive | 2011

REDUCED-STRESS BUMP-ON-TRACE (BOT) STRUCTURES

Yuh Chern Shieh; Han-Ping Pu; Yu-feng Chen; Tin-Hao Kuo

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Collaboration

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Chen-Shien Chen

TSMC

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Sheng-Yu Wu

TSMC

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Yen-Liang Lin

TSMC

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Yu-Jen Tseng

TSMC

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Chih-Horng Chang

TSMC

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Chang-Chia Huang

TSMC

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Chen-Hua Yu

TSMC

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Mirng-Ji Lii

TSMC

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Yu-feng Chen

TSMC

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Pei-Chun Tsai

TSMC

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