Petr Pfeifer

On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults

The rapidly growing world of FPGA devices offers important as well as interesting platforms for analyses of process scaling. It creates also new study opportunities in case of new process variations and degradation effects. Changes in parameters of FPGAs in time or under either power supply voltage or temperature variations result in timing variations or delays and may affect the final design quality and dependability. Such timing variations may result in delay faults, up to the final device or equipment malfunction or failure. FPGA designs must be carefully tested and simulated during the design phase. This area is well-covered by many papers and publications and being investigated again with the new processes coming every approximately 2 years. This paper investigates the area of effects caused by the FPGA chip design and metallization or design trade-offs. The paper presents interesting results obtained during various tests including the important values of the total delays caused by neighboring loaded SLICEs or locations in the FPGA. These results were obtained by a method of frequency and delay measurement, capable of delivering stable results in the range of 0.1ps (100fs), using only inexpensive tools and methods.

On measurement of parameters of programmable microelectronic nanostructures under accelerating extreme conditions (Xilinx 28nm XC7Z020 Zynq FPGA)

This paper presents a method and results from measurement of internal parameters of Xilinx XC7Z020 Zynq device - the programmable microelectronic nanostructures designed on 28 nm TSMCs technology. The presented method utilizes undersampling approach and a very easy way of processing of BRAM data streams. The presented flexible circuits have been used in various measurements of timing parameters delays in FPGAs, up to measurements or detection of the aging issues. The paper presents surprising overview of such measurements with the key result, that the usability of the latest 28 nm devices under accelerated conditions is strictly limited to lower frequencies or significantly lower temperatures. It also significantly limits the possibility of study of aging effects under accelerated conditions and might affect security applications. The paper extends the measurements and results available from previous technology nodes and tries to uncover new information and areas of the latest high-end technologies.

Delay-fault run-time XOR-less aging detection unit using BRAM in modern FPGAs

The reliability issue, including aging processes in modern devices with very fine structures and utilizing programmable technologies, being applied in high-performance or dependable systems in various safety, automotive or space applications, is sometimes very difficult to predict, measure or watch. The task is well-mastered in the world of ASIC, the situation is slightly different for FPGA devices. Modern FPGA devices incorporate number of true dual-port memory blocks with 8-T cells, hence offering new options. However, such blocks are typically used for data storage and processing purposes. This paper presents a new way of utilization of the RAM block (BRAM) for the delay fault detection purposes. The BRAM and a simple controller log risky transitions or delay fault events and may positively affect the overall reliability of the device as well as all the system.

A new area-efficient reconfigurable encoder architecture for flexible error detection and correction in dependable communication systems

Communication technologies are key and standard parts of most of todays integrated as well as field systems. Such technologies have experienced an explosive development during the last decades. More recently, short-distance communication systems have also been discussed as a way to connect embedded electronic systems in industrial applications. As industrial robots are assumed to be real-time and safety-critical in combination, test- and error correction technologies have to meet new challenges. However, many existing technologies for error correction are not able to manage multiple faults, are too slow in terms of encoding and decoding to satisfy industrial timing constraints. This paper introduces our PENCA architecture as a new concept of dependable fully configurable system, which promises a combination of reasonable overhead and relatively fast encoding, and ensuring high level of dependability, while keeping important flexibility, programmability and testability. Implementation results on Xilinx and Altera FPGA technologies are presented as well.

On performance estimation of a scalable VLIW soft-core in XILINX FPGAs

This paper presents performance estimations for a scalable VLIW soft-core in various XILINX FPGAs. It covers the low-cost low-power devices as well as the latest high-end FPGA families. The results represent the maximal clock frequency of the complete design including the processor core and the code and data memories. A scaling test has been done as well. In this case, the VLIW soft-core has incorporated various numbers of execution units and issue slots. It shows that the clock rate of the core scales much better with the number of execution units than proposed in estimations for standard-cell-based designs. It does not always create a lower clock rate of the design. Moreover, the highest possible clock rate shows some unexpected behaviour, when scaling the number of execution units. In some cases, a higher number of execution units cause no clock rate penalty. Finally, both ways of scaling the performance are compared with each other and some conclusions for a design space exploration of soft-cores are presented.

A new method for in situ measurement of parameters and degradation processes in modern nanoscale programmable devices

This paper presents a new method and results from measurement of internal parameters of programmable nanoscale circuits, namely Xilinx FPGA devices and especially Zynq SoC devices designed on 28nm TSMCs technology and older 45nm Spartan 6 device as well as Xilinx Virtex product lines. The method utilizes a new undersampling approach for frequency measurement and an easy way of processing BRAM data streams. The proposed flexible circuits have been used in various measurements of timing parameters and delays in FPGAs, including measurements or detection of the aging issues. The paper presents results of measurements under various core voltage values as performed on selected Xilinx FPGA platforms, including key results about limited usability of the latest 28nm devices under accelerated conditions and possibility of studying or mitigating aging effects in FPGAs. The paper presents rare results of experiments, real measurements and data available from current as well as previous technology nodes and it attempts to uncover new facts and areas of the latest high-end technologies, including the area of aging and degradation processes in general. The new methodology, presented approach and results can also be used in various dependable systems, including selected aerospace, medical, automotive or transportation ones. It is also directly and easily applicable to modern processor and multicore systems.

On comparison of robust configurable FPGA encoders for dependable industrial communication systems

Communication technologies have experienced an explosive development. Various short-distance communication systems have been used as a way of connecting embedded electronic systems in industrial applications. Test- and error detection or correction technologies have to meet new timing challenges and requirements in modern real-time and safety-critical systems, also set by Industry 4.0. Encoders using generator polynomials with linear-feedback shift registers (LFSRs) are the key parts of communication technologies, widely used in most of todays integrated as well as field systems. This paper presents a comparison of three basic ways of implementation of adaptive encoders configurable LFSRs using conventional configurable solutions, reconfigurable LUTs in SLICEMs in Xilinx FPGAs, and also encoders using standard Xilinx partial reconfiguration.

Iterative error correction with double/triple error detection

Wireless communication technologies have experienced an explosive development during the last two decades, based on the concept of cellular phones. More recently, short-distance wireless communication has also been discussed as a way to connect embedded electronic systems in industrial applications. Such systems have to work under stringent real-time constraints. For industrial in-door environments, we can a changing environment that produces serious flaws in wireless communication links occasionally. Therefore we explored new ways of forward error correction, which are fast in case of low error densities, but can deliver an enhanced multi-error detection capability if needed. A scheme of step-wise error correction using single error correction (SEC) step-by-step is feasible only, if double, triple and (with a high probability) multi-bit errors and errors on parity bits are detected and not mapped into false single bit error corrections. The paper give shows ways for expanding SEC schemes towards double and triple error detection, also including the vulnerability of extra parity bits.

Investigating diachrony of programmable microelectronic nanostructures

New technologies of design and manufacturing of advanced integrated circuits allow higher integration of complex structures in ultra-high nano-scale densities. The rapidly growing world of FPGA devices creates important platform for analyses of process scaling and new study opportunities in case of new process variations and degradation effects. However the real devices are not the ideal ones and they are subjects of aging of the internal nanostructures. Changes in parameters of FPGAs in time, or under either power supply voltage or temperature variations, can result in significant delays and may affect the final design quality and dependability. Such timing variations may result in delay faults, up to the final device or equipment malfunction or failure. Especially the world of ASIC devices is comprehensively investigated again and again with the new processes coming every (approximately) 2 years. This paper presents an unusual solution of the aging measurement, analysis and test unit, based on especially designed ring oscillators and utilization of the internal block RAMs (BRAM) in Xilinx FPGAs, selected from 65 nm down to the 40 nm technology node.

Forward error correction in wireless communication systems for industrial applications

Industrial manufacturing is more and more based groups of robots in production cells. The robots consist of moving, bending and rotating arms with multiple joints. Cables that connect sections of robots undergo heavy stress from stretching and twisting, resulting in wear-out and failure. Replacing cables on robots by wireless communication therefore is an alternative that has been investigated for some time. Unfortunately, communication channels in industrial environments suffer from some adversary effect. First, standard industrial communication networks work on rigid time frames which limit allowed latencies in communication systems considerably. Second, multiple path propagation and destructive interferences make such communication channels sensitive to fading problems. Therefore forward error correction (FEC) that can compensate massive variations of signal strength becomes a must. On the other hand, forward error correction using known methods such as BCH codes, Reed-Solomon codes, turbo codes and low-density parity checks (LDPC) is not very fast by nature. Codes for single effort correction and double error detection (SEC-DED-codes) such as Hamming code and Hsiao code are fast, but they are not powerful enough to correct multiple bit errors or restore missing symbols, unless they are applied in a step-wise approximation. PENCA (programmable encoding architecture) is a new approach in multiple error detection and correction which is, at present based on BCH codes, reasonably fast by parallel hardware. Furthermore, it allows for adaptive error correction, based on the quality of the channel, therefore providing a better overhead / performance ratio than methods that are based on a fixed number of allowed error bits in a symbol, tailored to handle worst-case conditions. PENCA is currently becoming part of an industrial communication systems developed in the ParSeC project, which is a cooperative effort of industries, universities and research institutes, funded by the German Ministry of Research and Education (BMBF).