Todd C. Bailey

Leveraging advanced data analytics, machine learning, and metrology models to enable critical dimension metrology solutions for advanced integrated circuit nodes

Abstract. Integrated circuit (IC) technology is changing in multiple ways: 193i to extreme ultraviolet exposure, planar to nonplanar device architecture, from single exposure lithography to multiple exposure and directed self-assembly (DSA) patterning, and so on. Critical dimension (CD) control requirement is becoming stringent and more exhaustive: CD and process windows are shrinking, three-sigma CD control of <2  nm is required in complex geometries, and a metrology uncertainty of <0.2  nm is required to achieve the target CD control for advanced IC nodes (e.g., 14, 10, and 7 nm nodes). There are fundamental capability and accuracy limits in all the metrology techniques that are detrimental to the success of advanced IC nodes. Reference or physical CD metrology is provided by atomic force microscopy (CD-AFM) and TEM while workhorse metrology is provided by CD-SEM, scatterometry, and model-based infrared reflectrometry (MBIR). Precision alone is not sufficient for moving forward. No single technique is sufficient to ensure the required accuracy of patterning. The accuracy of CD-AFM is ∼1  nm and the precision in TEM is poor due to limited statistics. CD scanning electron microscopy (CD-SEM), scatterometry, and MBIR need to be calibrated by reference measurements for ensuring the accuracy of patterned CDs and patterning models. There is a dire need for a measurement with <0.5  nm accuracy and the industry currently does not have that capability with inline measurements. Being aware of the capability gaps for various metrology techniques, we have employed data processing techniques and predictive data analytics, along with patterning simulation and metrology models and data integration techniques to selected applications demonstrating the potential solution and practicality of such an approach to enhance CD metrology accuracy. Data from multiple metrology techniques have been analyzed in multiple ways to extract information with associated uncertainties and integrated to extract the useful and more accurate CD and profile information of the structures. This paper presents the optimization of scatterometry and MBIR model calibration and the feasibility to extrapolate not only in design and process space but also from one process step to a previous process step. A well-calibrated scatterometry model or patterning simulation model can be used to accurately extrapolate and interpolate in the design and process space for lithography patterning where AFM is not capable of accurately measuring sub-40 nm trenches. The uncertainty associated with extrapolation can be large and needs to be minimized. We have made use of measurements from CD-SEM and CD-AFM, along with the patterning and scatterometry simulation models to estimate the uncertainty associated with extrapolation and the methods to reduce it. For the first time, we have reported the application of machine learning (artificial neural networks) to the resist shrinkage systematic phenomenon to accurately predict the preshrink CD based on supervised learning using the CD-AFM data. The study lays out various basic concepts, approaches, and protocols of multiple source data processing and integration for a hybrid metrology approach. Impacts of this study include more accurate metrology, patterning models, and better process controls for advanced IC nodes.

Reflectivity-induced Variation in Implant Layer Lithography

Scaling of designs to the 45nm and future nodes presents challenges for block level lithography. Shrinking distances between devices drive aggressive resist placement tolerances, challenging the ability to control critical dimension (CD). In particular, the potential variation in shallow trench isolation oxide may result in variation of resist profile and CD, thereby affecting edge placement accuracy. Potential sources of this include wafer-to-wafer or within-wafer STI trench depth variations, and STI CMP variations that may be induced by active area pattern density fluctuations. Some other potential sources of CD fluctuation include oxide sidewall variation, and implant level overlay or CD errors modulating the proximity to the oxide sidewall. Depending on the actual variation of isolation oxide and the exposure latitude of the resist, the CD variations simply from oxide variation may consume a large portion of the CD budget. Several examples are given of variations in resist profile and CD arising from these substrate effects. The CD uniformity of a test structure was shown to decrease dramatically with the addition of a BARC to the resist stack, most likely due to the suppression of substrate reflectivity variations. Simulations performed using Panoramic Technologies software demonstrated the potential sensitivity of the factors outlined above on CD and profile errors. A comparison of simulated vs. experimental results is made for a case of intentional overlay error, showing the failure mode of the resist profile as the mask edge passes from STI to the active area. The simulations using a full physical model provided with the simulation software predict a resist foot forming over the active area, which was confirmed experimentally.

Substrate aware OPC rules for edge effect in block levels

Implant level photolithography processes are becoming more challenging each node due to everdecreasing CD and resist edge placement requirements, and the technical challenge is exacerbated by the business need to develop and maintain low-cost processes. Optical Proximity Correction (OPC) using models created based on data from plain silicon substrate is not able to accommodate the various real device/design scenarios due to substrate pattern effects. In this paper, we show our systematic study on substrate effect (RX/STI) on implant level lithography CD printing. We also explain the CD variation mechanism and validate by simulation using well calibrated physical resist model. Based on the results, we propose an approach to generate substrate-aware OPC rules to correct for such substrate effects.

3D physical modeling for patterning process development

In this paper we will demonstrate how a 3D physical patterning model can act as a forensic tool for OPC and ground-rule development. We discuss examples where the 2D modeling shows no issues in printing gate lines but 3D modeling shows severe resist loss in the middle. In absence of corrective measure, there is a high likelihood of line discontinuity post etch. Such early insight into process limitations of prospective ground rules can be invaluable for early technology development. We will also demonstrate how the root cause of broken poly-line after etch could be traced to resist necking in the region of STI step with the help of 3D models. We discuss different cases of metal and contact layouts where 3D modeling gives an early insight in to technology limitations. In addition such a 3D physical model could be used for early resist evaluation and selection for required ground-rule challenges, which can substantially reduce the cycle time for process development.

Message to the undecided - Using DUV dBARC for 32 nm node implants

In recent years, implant (block) level lithography has been transformed from being widely viewed as non-critical into one of the forefronts of material development. Ever-increasing list of substrates, coatings and films in the underlying stack clearly dictates the need for new materials and increased attention to this challenging area. Control of the substrate reflectivity and critical dimension (CD) on topography has become one of the key challenges for block level lithography and is required in order to meet their aggressive requirements for developing 32nm technology and beyond. The simulation results of wet-developable bottom anti-reflective coating (dBARC) show better reflectivity control on topography than the conventional top anti-reflective materials (TARCs), and make a convincing statement as to viability of dBARC as a working solution for block level lithography.1 Wet-developable BARC by definition offers substrate reflectivity and resist adhesion control, however there is a need to better understand the fundamental limitations of the dBARC process in comparison to the TARC process. In addition, some specific niche dBARC applications as facilitating adhesion to challenging substrates, such as capping layers in the high-k metal gate (HK/MG) stack, can also be envisioned as most imminent dBARC applications.2 However, most of the engineering community is still indecisive to use dBARC in production, bound by uncertainties of the robustness and lack of experience using dBARC in production. This work is designed to inspire more confidence in the potential use of this technology. Its objective is to describe testing of one of dBARC materials, which is not a photosensitive type, and its implementation on 32nm logic devices. The comparison between dBARC and TARC processes evaluates impacts of dBARC use in the lithographic process, with special attention to OPC behavior and reflectivity for controlling CD uniformity. This work also shows advantages and future challenges of dBARC process with several 248nm and 193nm resists on integrated wafers, which have shallow trench isolation (STI) and poly gate pattern topography.

Multitechnique metrology methods for evaluating pitch walking in 14 nm and beyond FinFETs

Abstract. Integrated circuits from 22-nm node and beyond utilize many innovative techniques to achieve features that are well beyond the resolution limit of 193-nm immersion lithography. The introduction of complex three-dimensional structures in device design presents additional challenges that require more sophisticated metrology with high accuracy and precision. One such example is pitch walking induced by multiple-patterning techniques. Quantification of pitch walking has traditionally been a challenge. We present two ways of detecting pitch walking using optical and x-ray techniques. In scatterometry, this work investigates the feasibility of nonorthogonal azimuth angle spectroscopic reflectometry setups for fin pitch walking measurements, which is useful for in-line monitoring in 14-nm node microelectronics manufacturing. Simulations show a significant improvement in pitch walking sensitivity using 45-deg azimuth scan. Other relevant considerations for pitch walking modeling in scatterometry, such as parameter correlations, are also discussed. Another approach is using high-resolution x-ray diffraction (HRXRD) to measure the diffraction peaks from crystalline fins. The onset of pitch walking is determined by the appearance of a shifted subset of peaks in the diffraction spectrum. Information about the fin profiles, e.g., sidewall angle, critical dimension, height, and pitch walking, can be obtained from the resultant diffraction pattern. Note that in HRXRD measurements, each critical parameter is a unique element in the Reciprocal Space Map (RSM) and no correlations between parameters exist. We will discuss the results from measurements using the two techniques and how the combination of the two techniques can give complete information about the fins needed for in-line monitoring.

Novel in-line metrology methods for Fin pitch walking monitoring in 14nm node and beyond

Integrated circuits from 22nm node and beyond utilize many innovative techniques to achieve features that are well beyond the resolution limit of 193nm immersion lithography. The introduction of complex 3D structures in device design presents additional challenges that require more sophisticated metrology with high accuracy and precision. One such example is pitch walking induced by multiple-patterning techniques. Quantification of pitch walking has traditionally been a challenge. In this paper, we present two ways of detecting pitch walking using optical and X-ray techniques. In scatterometry, this work investigates the feasibility of non-orthogonal azimuth angle spectroscopic reflectometry setups for Fin pitch walking measurements, which is useful for in-line monitoring in 14nm node microelectronics manufacturing. Simulations show a significant improvement in pitch walking sensitivity using 45 degree azimuth scan. Other relevant considerations for pitch walking modeling in scatterometry, such as parameter correlations, are also discussed. Another approach is using high-resolution X-ray diffraction (HRXRD).Which is sensitive to the crystalline films. Pitch walking is seen as additional peaks in the diffraction and the intensities can be used to quantify the pitch walking. In addition, additional information about the Fin profiles, e.g. sidewall angle, CD and height, can be obtained. Note that in HRXRD measurements, all the parameters are deconvolved from the pitch walking. In this paper, we will discuss the results from measurements using the two techniques and how the combination of the two techniques can give complete information about the fins needed for in-line monitoring.

Three-dimensional physical photoresist model calibration and profile-based pattern verification

In this paper, we report large scale three-dimensional photoresist model calibration and validation results for critical layer models that span 32 nm, 28 nm and 22 nm technology nodes. Although methods for calibrating physical photoresist models have been reported previously, we are unaware of any that leverage data sets typically used for building empirical mask shape correction models. . A method to calibrate and verify physical resist models that uses contour model calibration data sets in conjuction with scanning electron microscope profiles and atomic force microscope profiles is discussed. In addition, we explore ways in which three-dimensional physical resist models can be used to complement and extend pattern hot-spot detection in a mask shape validation flow.

Methodology for determining critical dimension scanning electron microscope measurement condition of sub-20 nm resist patterns for 0.33 NA extreme ultraviolet lithography

Abstract. A methodology to determine the optimum measurement condition of extreme ultraviolet (EUV) resist patterns in a critical dimension scanning electron microscope has been established. Along with many parameters that need to be optimized simultaneously, there are conflicting requirements of small resist shrinkage and high measurement precision. To overcome these difficulties, we have developed a methodology for ArF resist patterns from shrinkages and precisions predicted by the Taguchi method. In this study, we examined the extendibility of the methodology to sub-20 nm EUV resist patterns. The predicted shrinkage by the Taguchi method for an 18 nm EUV resist pattern showed a large prediction error due to its different dependence on acceleration voltage from ArF, so we used the shrinkage curve to predict shrinkage instead of the Taguchi method, as shrinkage depends only on irradiated electron dose. In contrast, precision can be predicted well by the Taguchi method as with ArF. We propose a methodology that consists of separate prediction procedures for shrinkage and precision using the shrinkage curve and Taguchi method, respectively. The proposed method was applied to an 18-nm EUV resist pattern. The optimum measurement condition with shrinkage of 1.5 nm and precision of 0.12 nm was determined.

Machine learning and predictive data analytics enabling metrology and process control in IC fabrication

Integrate circuit (IC) technology is going through multiple changes in terms of patterning techniques (multiple patterning, EUV and DSA), device architectures (FinFET, nanowire, graphene) and patterning scale (few nanometers). These changes require tight controls on processes and measurements to achieve the required device performance, and challenge the metrology and process control in terms of capability and quality. Multivariate data with complex nonlinear trends and correlations generally cannot be described well by mathematical or parametric models but can be relatively easily learned by computing machines and used to predict or extrapolate. This paper introduces the predictive metrology approach which has been applied to three different applications. Machine learning and predictive analytics have been leveraged to accurately predict dimensions of EUV resist patterns down to 18 nm half pitch leveraging resist shrinkage patterns. These patterns could not be directly and accurately measured due to metrology tool limitations. Machine learning has also been applied to predict the electrical performance early in the process pipeline for deep trench capacitance and metal line resistance. As the wafer goes through various processes its associated cost multiplies. It may take days to weeks to get the electrical performance readout. Predicting the electrical performance early on can be very valuable in enabling timely actionable decision such as rework, scrap, feedforward, feedback predicted information or information derived from prediction to improve or monitor processes. This paper provides a general overview of machine learning and advanced analytics application in the advanced semiconductor development and manufacturing.