Thuy B. Dao

Through Silicon Via stress characterization

In this paper, we will present Micro Raman stress data of Through Silicon Vias (TSV) with different shapes and sizes & spacing, and discuss design considerations.

Micro-scale measurement and modeling of stress in silicon surrounding a tungsten-filled through-silicon via

The stress in silicon surrounding a tungsten-filled through-silicon via (TSV) is measured using confocal Raman microscopy line scans across the TSV both before and after etch removal of an oxide stack used as a mask to define the TSV during fabrication. Stress in the silicon arose in response to both athermal deposition and thermal expansion mismatch effects. The complex three-dimensional stress and strain field in silicon surrounding the TSV is modeled using finite element analysis, taking into account both athermal and thermal effects and the elastic anisotropy of silicon. Comparison of the measurements and model results shows that no one component of the stress tensor correlates with the Raman peak shift generated by the deformed silicon. An analysis is developed to predict the Raman shift in deformed silicon that takes into account all the components of the stress or strain tensor; the results of the model are then used as inputs to the analysis for direct comparison with measured peak shifts as a fun...

Progress and challenges of tungsten-filled through-silicon via

Through Silicon Via (TSV) has been used for back-end packaging and more recently, for front end active device integration. In this work we report recent progress and challenges for via cleaning, via filling and wafer bow / stress monitoring. Furthermore, the importance of preparation technique for accurate characterization of tungsten-filled TSV profile will be presented.

Thermo-mechanical stress characterization of tungsten-fill through-silicon-via

Thermo-mechanical stress of tungsten-filled (W-fill) through-silicon-via (TSV) is strongly depending on via shape, size and inter-via spacing, which places constraints on TSV design, including 2-D integrated circuit layout and 3-D structure profile. This paper summarizes these constraints and co-relations among thick (up to 1.2µm) tungsten (W) film, W-fill TSV, and surrounding silicon structures, using Flexus bowing measurement, Wright etch method, and also 3-D TSV stress simulations. In this study, the stress was found to be primarily tensile, and tended to be much higher along the longitudinal ends of the TSV compared to the longitudinal side wall. For an isolated TSV of given width and depth: with 30µm length the stress is 45% greater compared to the case of 7µm length. For an array of TSV with given length, width, and depth: larger spacing along the longitudinal axis (length directions) resulted in 35% lower stress at the longitudinal ends of the TSV, while smaller spacing along the transverse axis (width directions) of the TSV resulted in a 46% lower tensile stress. However, along the longitudinal side walls, the tensile stress increases by 200 MPa as the spacing along the transverse axis decreases between neighboring TSV.

Through-Silicon-Via stress 3D modeling and design

Through-Silicon-Via (TSV) processing is critical to 3D chip stacked integrated circuit (IC) technology. The understanding and management of the induced stresses in silicon due to coefficient of thermal expansion (CTE) mismatch is critical for the successful implementation of this process in circuit design and production. Most TSVs in these applications are copper (Cu) filled. Analysis of Cu-filled TSV induced stress has been reported by Okoro et. al [1], and the proposed stress measurement and model has been reported by Chidambaram et. al. [2].

Evaluation of non-destructive etch depth measurement for through silicon vias

Through-Silicon-Via depth inline monitoring is one of the key requirements for implementing TSV technology into high volume production. The Tamar tool using IR from the backside of wafer is demonstrated to have the capability to provide non-destructive inline monitoring of trench depth after plasma etch, even when the backside wafer surface is rough. However, the etch profile is found to be critical to the effectiveness of this tool. A flat TSV bottom with a minimum of at least 1um in width is required for accurate and repeatable measurements.

Integration challenges of new materials and device architectures for IC applications

In this paper, we will detail the issues with new materials being introduced into CMOS devices and present some potential solutions to enable high performance and low power CMOS for the 65nm node and beyond.

Characterization of onset tunneling voltage (V onset ) walkout in high-voltage deep trench isolation on SOI

Deep trench isolation (DTI) with “walkout” onset tunneling voltage (V_onset) can cause serious confusion for performance enhancement and process optimization in technology development. The ordinary breakdown voltage (BV) “walkout” phenomenon occurs when a premature avalanche breakdown injects high energy carriers into an oxide so that subsequent stress may causes an increase in oxide breakdown voltage [1]. However, the increase in the V_onset with multiple I-V sweeps for our DTI structures are of very different origins. This is the first report on the characterization of V_onset “walkout” in HV deep trench isolation (DTI) on SOI.

Improved deep trench isolation breakdown voltage for SmartMOS

To achieve higher voltage analog and power devices, the deep trench isolation breakdown voltage must withstand the higher operating voltages. Optimization of deep trench etch to produce a straighter etch profile enable a void free poly filled trench, adding HF clean improve liner oxide film quality and changing liner oxidation process change the fill profile enable the oxide liner thickness to increase result in increase in the deep trench isolation (DTI) breakdown voltage.

STI fill effect on poly-poly comb IL

Increasing ETD ratio for HDP oxide from 0.10 to 0.16 resulted in increasing film stress; film became more compressive. An increase in HF RF setting typically causes an increase in sputtering that may cause additional process induced damage or defects resulting in poorer oxide film quality, but the oxide wet etch rate ratio remain similar with increase in ETD which indicated no change in oxide quality. However, increasing etch to deposition ratio of HDP CVD film was demonstrated to improve gap fill of STI as indicated by a reduction in poly-poly comb shorts.