Tom Borgers

High performance Hybrid and Monolithic Backside Thinned CMOS Imagers realized using a new integration process

Hybrid and monolithic thinned backside illuminated CMOS imagers operating at full depletion at low substrate voltages were developed. The combination of a 50 mum EPI layer with varying doping concentration and trenches to reduce crosstalk is unique. All thin wafer processing is performed on 200 mm wafers using a specially developed temporary carrier process. As a result, working imagers exhibiting high pixel yield, high quantum efficiency and low dark current are demonstrated

Reduction of Electrical Crosstalk in Hybrid Backside Illuminated CMOS Imagers using Deep Trench Isolation

Hybrid backside illuminated CMOS imagers with zero pixel-to-pixel electrical crosstalk were developed. The application of highly doped polysilicon filled high aspect ratio trenches between pixels to reduce crosstalk is unique. These 1¿m wide 50¿m deep trenches enforce a lateral drift field between pixels, which counteracts diffusion and drastically reduces electrical crosstalk. Quantitative crosstalk characterization of trenched and non-trenched imagers is presented.

Multi-wire interconnection technologies weaving the way for back contact and bifacial PV modules

We introduce two multi-wire cell interconnection concepts where the solder-coated metal wires are incorporated in a woven fabric with insulating fibers. Woven fabrics enable the integration of thermal stress relief features currently lacking from other similar technologies. We present the adaptation of the interconnection technology both to back- and two-side contacted cells by optimizing the woven fabric materials and properties. For back-contacted cells the metal wires are combined with glass fiber for electrical insulation, while the fabric for two-side contacted cells is made of encapsulant ribbons and metal wires to combine the two functionalities in one sheet. We demonstrate functional laminates with both concepts.