Jonathan Govaerts

Fabrication Processes for Embedding Thin Chips in Flat Flexible Substrates

These days, a lot of effort is being put in making electronic devices lighter and compacter, as the electronics market is rapidly expanding with all sorts of portable devices for home and everyday use. In this paper, a technology for embedding thin chips in flexible substrates is proposed that could be the next step for further reducing weight, while at the same time enhancing mechanical flexibility of the electronic circuitry. All stages in the technologys development cycle are discussed: from technology flow, test design and actual fabrication, to process optimization and characterization of the results. An outlook on the following steps of this technology is discussed in the conclusion.

Improving the Quality of Epitaxial Foils Produced Using a Porous Silicon-based Layer Transfer Process for High-Efficiency Thin-Film Crystalline Silicon Solar Cells

A porous silicon-based layer transfer process to produce thin (30-50 μm) kerfless epitaxial foils (epifoils) is a promising approach toward high-efficiency solar cells. For high efficiencies, the epifoil must have high minority carrier lifetimes. The epifoil quality depends on the properties of the porous layer since it is the template for epitaxy. It is shown that by reducing the thickness of this layer and/or its porosity in the near-surface region, the near-surface void size is reduced to <;65 nm and in certain cases achieve a 100 nm-thick void-free zone below the surface. Together with better void alignment, this allows for a smoother growth surface with a roughness of <;35 Å and reduced stress in the porous silicon. These improvements translate into significantly diminished epifoil crystal defect densities as low as ~420 defects/cm 2. Although epifoils on very thin porous silicon were not detachable, a significant improvement in the lifetime (diffusion length) of safely detachable n-type epifoils from ~85 (~300 μm) to ~195 μs (~470 μm) at the injection level of 10 15/cm 3 is achieved by tuning the porous silicon template. Lifetimes exceeding ~350 μs have been achieved in the reference lithography-based epifoils, showing the potential for improvement in porous silicon-based epifoils.

18% Efficiency IBC Cell With Rear-Surface Processed on Quartz

In order to relax the mechanical constraints of processing thin crystalline Si wafers into highly efficient solar cells, we propose a process sequence, where a significant part of the process is done on module level. The device structure is an interdigitated-back-contact cell with an amorphous silicon back surface field. The record cell reaches an independently confirmed efficiency of 18.4%. Although the device deserves further optimization, the result shows the compatibility of processing on glass with efficiencies exceeding 18%, which opens the door to a high-efficiency solar cell process where the potentially thin wafer is attached to a foreign carrier during the full processing sequence.

High-quality epitaxial foils, obtained by a layer transfer process, for integration in back-contacted solar cells processed on glass

Foil creation by lifting off a thin layer of a high quality silicon substrate is one of the promising substitutes for wafer sawing to create substrates thinner than 100 μm. The porous silicon-based layer transfer process is a well known method to obtain high quality foils. Despite a number of convincing lab-based solar cell show-cases, there is no breakthrough of this technology at (semi)-industrial level, because of the poor yield of processing free standing foils. This paper presents a method to fabricate back contacted solar cells based on epitaxial foils avoiding processes on free-standing foils. First, a porous silicon layer is electrochemically etched, acting as a weak sacrificial layer to detach the foil that is epitaxially grown on top of the porous silicon layer. Characterization of the epitaxial foils shows a good crystalline quality and an effective lifetime around 100 μs. Those results give indications that the obtained foils are well suited for solar cell fabrication. Front-side processing is done while the epitaxial foil is still attached to its parent substrate. A good yield is obtained for epitaxial foils that underwent the front-side processing sequence consisting of wet chemical texturing, FSF formation, passivation and ARC deposition. Afterwards, the front-side of the foil is bonded to a glass carrier and the foil is detached from its parent substrate. Silicone adhesives are used for this permanent bond. The rear-side of the solar cell is processed while bonded to glass. Therefore, only low temperature processes (<;200°C) can be used. So far, the rear-side processing sequence was performed on Float-zone reference wafers as a proof of concept resulting in a confirmed maximum efficiency of 18.4%. The rear-side processing sequence still needs to be applied on epitaxial foils.

Heterojunction Interdigitated Back-Contact Solar Cells Fabricated on Wafer Bonded to Glass

Future wafer-based silicon solar cells will be fabricated on thin (<;140 μm) wafers. However, technologies to handle thin wafers during cell processing are not yet available for industry. In this paper, a flow to handle thin wafers during rear side cell processing is developed and demonstrated on 4-in 200 μm-thick wafers. The flow involves bonding the wafers to glass after front-side processing followed by a low-temperature p-n heterojunction formation on the rear side. 2.5 × 2.5 cm2 amorphous/crystalline silicon heterojunction interdigitated back-contact solar cells are fabricated by use of lithography while bonded to glass, and they show an efficiency of up to 17.7%. Shunts, infrared light absorption, and rear side interface passivation are identified as the main efficiency losses. Dedicated experiments suggest that the passivation losses are related to the degradation of the adhesive during wafer cleaning. Hence, methods to improve the compatibility of the adhesive with the cleaning process are discussed.

Fine-Pitch Capabilities of the Flat Ultra-Thin Chip Packaging (UTCP) Technology

This paper describes the fine-pitch interconnection capabilities of the ultra-thin chip packaging (UTCP) technology, a technology under development for embedding thin chips in a flexible polyimide (PI) substrate. It allows for fully flexible electronics, as the rigid chips are thinned down to 20-30 ¿m, at which point they become truly flexible themselves. This way, instead of just a flexible substrate with rigid components assembled on top, the entire circuitry can be incorporated inside a 30-40 ¿m thin chip package. The paper briefly introduces the technologys background with a short description of the fabrication process. Building on the developments already achieved, some further optimizations are discussed, and the technology is tested for its fine-pitch interconnection capabilities using test chips with four-point probe and daisy chain patterns, with a pitch down to 40 ¿m. The possibility to package several chips in the same substrate is investigated, as well, and finally an outlook on future experiments is briefly discussed.

Assembly of ultra-thin chip packages (UTCPs) for enhanced flexibility of flexible displays

In this paper, a setup has been designed to test the assembly of UTCPs onto patterned flexible substrates. The assembly is carried out with Anisotropic Conductive Film (ACF) bonding, offering the advantages of fine pitch connection possibilities and low-temperature curing, often a requirement for flexible display backplanes. Furthermore, the UTCP has been designed with contacts at the four sides of the (square) package, and a matching thermode allows for all four sides to be bonded at the same time.

Thermo-mechanical challenges of advanced solar cell modules

This paper firstly summarizes the process flow developed at IMEC to integrate and interconnect thin back-contact solar cells into modules. Secondly, the process flow is simulated by Finite Element Modelling to determine critical process steps that may lead to early failures. A virtual Design of Experiment (DOE) is used to determine the best geometry and materials properties in order to minimise the induced stresses in the cells and the interconnections. The variables of this DOE are the silicon, the glue and the encapsulant thickness and the Elastic Modulus of the glue and encapsulant. The results of this DOE are presented in forms of Response Surface Models and it is observed that Youngs Modulus of encapsulant and the thickness of the solar cells are the mayor contributors to the stresses in the silicon cells. Furthermore, an analysis of the changes in distance between adjacent cells at different temperatures indicates that the stiffness of the encapsulant material will play an important role on the mechanical behavior of the metallic solar cells interconnections.

Multiple chip integration for flat flexible electronics

These days, there is a lot of interest for making electronic devices lighter and compacter, as the electronics market is rapidly expanding with all sorts of portable devices for home and everyday use. Here, a technology for embedding single thin chips in flexible substrates is further investigated so that several chips might be integrated within the same substrate. This technology offers the possibility of reducing weight, while at the same time enhancing the mechanical flexibility of the electronic circuitry. Such an integration is particularly interesting in the area of flexible displays, where the flexibility of the display is too often hampered by the rigidity of its driving electronics.

16.4: Ultra-Thin Chip Packaging (UTCP): A Promising Technology for Future Flexible Display Interconnection

With several flexible display technologies sprouting up, the driving electronics seem to become the limiting factors in the bendability of any flexible display system. The idea of adapting existing interconnection technologies is discussed. Finally, ultra-thin chip packaging is proposed to bypass this limitation imposed by the rigidity of the driver electronics.