Wouter Ruythooren

3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias

Using standard single damascene type techniques on bulk-Si, combined on one hand with extreme wafer thinning and on the other with Cu-Cu thermo-compression bonding technology, the paper demonstrate yielding 10k through-wafer 3D-via chains with a via pitch of 10μm for a via diameter of 5μm. The bonded contacts exhibit shear strengths exceeding 40MPa. Measurements indicate there is no significant contact resistance at the Cu-Cu bonded interface: within measurement accuracy, the 4-point via chain resistance is consistent with bulk Cu resistivity

Improvement of AlGaN∕GaN high electron mobility transistor structures by in situ deposition of a Si3N4 surface layer

We have made AlGaN∕GaN high electron mobility transistors with a Si3N4 passivation layer that was deposited in situ in our metal-organic chemical-vapor deposition reactor in the same growth sequence as the rest of the layer stack. The Si3N4 is shown to be of high quality and stoichiometric in composition. It reduces the relaxation, cracking, and surface roughness of the AlGaN layer. It also neutralizes the charges at the top AlGaN interface, which leads to a higher two-dimensional electron-gas density. Moreover, it protects the surface during processing and improves the Ohmic source and drain contacts. This leads to devices with greatly improved characteristics.

3D stacked IC demonstration using a through Silicon Via First approach

We report for the first time the demonstration of 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV). The Cu TSV process is inserted between contact and M1 of our reference 0.13 mum CMOS process on 200 mm wafers. The top die is thinned down to 25 mum and bonded to the landing wafer by Cu-Cu thermo-compression. Both top and landing wafers contain CMOS finished at M2 to evaluate the process impact both FEOL and BEOL. The results confirm no degradation of the FEOL performance. The functionality of various ring oscillator topologies that include inverters distributed over both top and bottom dies connected through TSVs demonstrates excellent chip integrity after the TSV and 3D stacking process.

Through-silicon via and die stacking technologies for microsystems-integration

The highest integration density of microsystems can be obtained using a 3D-stacking approach, where each layer of the stack is realized using a different technology, which may include sensors, imagers, rf and MEMS technologies. A key challenge is however to perform such stacking in a cost-effective manner. In this paper, a novel 3D TSV and 3D stacking technologies will be presented. Application examples are MEMS packaging and heterogeneous integration of imaging devices.

Sloped Through Wafer Vias for 3D Wafer Level Packaging

Through silicon via (TSV) technology is one of the critical and enabling technologies for 3D chip stacking. Many TSV approaches that have been demonstrated are application specific; and there is a great need for generic solutions. This work describes the design, fabrication and characterization of a TSV technology for silicon substrates where the interconnects are fabricated typically after standard CMOS processing and can be applied to any silicon based technology. This so-called 3D Wafer Level Packaging (3D-WLP) technology die stacking is based on a the thinning first, via last approach: the via is fabricated from the backside of a thinned wafer. Plasma etching of the wafer is used to achieve sloped profde which allows the conformal deposition of the dielectric layer and copper seed metallization. The vias are isolated from the substrate using polymer dielectrics; and spray coating of photoresist is used to pattern the dielectric within the vias. Electrical connection between the front and the back of the wafer is achieved by partial filling of the vias with copper. All processes employed in the fabrication of sloped through wafer vias are performed using standard wafer handling and at low temperature (< 250degC) for post CMOS compatibility. Various dimensions of TSVs are fabricated and electrically characterized by four point measurements. The measurements and calculations on daisy chains connecting a number vias in series show that the via resistance is in the range of 20-30mOmega depending on the via size. We believe that this generic 3D-WLP via approach is suitable for many 3D applications.

Electrodeposition for the synthesis of microsystems

Electroplating is an emerging technique for the production of microsystems. This is due to advantages such as high rate of deposition, high resolution, high shape fidelity, simple scalability, and good compatibility with existing processes in microelectronics. Materials ranging from high-conductivity metals over soldering connections to ferromagnets can be deposited. In this paper the basics of electroplating are reviewed and examples of recent applications of electroplating in the processing of microsystems are presented.

The role of Al on Ohmic contact formation on n-type GaN and AlGaN/GaN

A standard metallization scheme for the formation of Ohmic contacts on n-type GaN does exist. It has the following multilayer structure: Ti∕Al∕metal∕Au. Ti is known to extract N out of the GaN. This leaves a high density of N vacancies (donors) near the interface pinning the Fermi level. The created tunnel junction is responsible for an Ohmic contact behavior. Au is deposited as the final metal layer to exclude oxidation of the contact and the metal should limit the diffusion of Au into the layers below and vice versa. Al in the metallization scheme is known to improve the contact resistance, but the reason why has not been reported yet. We studied Ti and Ti∕Al contacts on GaN and AlGaN∕GaN as a function of annealing temperature by transmission electron microscopy. The role of Al in the metal multilayer, and of Al in the AlGaN on the Ohmic contact formation, has been determined. The latter result indicates that the standard metallization scheme for GaN cannot be simply transferred to AlGaN∕GaN structures.

Simultaneous Cu-Cu and Compliant Dielectric Bonding for 3D Stacking of ICs

This paper, for the first time reports the 3D stacking and interconnection of an extremely thinned IC by simultaneous Cu-Cu thermocompression and compliant glue layer bonding. Inclusion of a compliant glue layer serves reinforcement of the mechanical stability of the stack in areas where the inter-die interconnect density is low. It also enables separation in time of stacking on one hand and bonding on the other hand, thus enabling collective bonding after die to wafer stacking. We demonstrate electrically yielding 10 k through-wafer via chains without observable impact of the dielectric glue layer on the via chain resistance.

Improved Thermal Performance of AlGaN/GaN HEMTs by an Optimized Flip-Chip Design

AlGaN/GaN high electron mobility transistors (HEMT) on sapphire substrates have been studied for their potential application in RF power applications; however, the low thermal conductivity of the sapphire substrate is a major drawback. Aiming at RF system-in-a-package, the authors propose a flip-chip-integration approach, where the generated heat is dissipated to an AlN carrier substrate. Different flip-chip-bump designs are compared, using thermal simulations, electrical measurements, micro-Raman spectroscopy, and infrared thermography. The authors show that a novel bump design, where bumps are placed directly onto both source and drain ohmic contacts, improves the thermal performance of the HEMT

Changing Superfilling Mode for Copper Electrodeposition in Blind Holes from Differential Inhibition to Differential Acceleration

Blind holes 5 μm diam and 25 μm in depth were filled with electrodeposited copper. Before electrodeposition, the blind holes were fully metallized with a copper seed layer or with a thin sputtered Ta layer deposited on top of the copper seed layer. Filling of partially Ta-capped features was three times faster than filling fully metallized features. For fully metallized features, the growth mode for copper electrodeposition is dominated by diffusion adsorption of a leveling agent. For partially Ta-capped surfaces, the growth mode was modified to differential acceleration through accumulation of an accelerating species at the bottom of features.