Tomoharu Tanaka

A dynamic analysis of the Dickson charge pump circuit

Dynamics of the Dickson charge pump circuit are analyzed. The analytical results enable the estimation of the rise time of the output voltage and that of the power consumption during boosting. By using this analysis, the optimum number of stages to minimize the rise time has been estimated as 1.4 N/sub min/, where N/sub min/ is the minimum value of the number of stages necessary for a given parameter set of supply voltage, threshold voltage of transfer diodes, and boosted voltage. Moreover, the self-load capacitance of the charge pump, which should be charged up at the same time as the output load capacitance of the charge pump, has been estimated as about one-third of the total charge pump capacitance. As a result, the equivalent circuit of the charge pump has been modified. The analytical results are in good agreement with simulation by the iteration method, typically within 10% for the rise time and within 2% for the power consumption. In the case of a charge pump with MOS transfer transistors, the analytical results of the rise time agree with the SPICE simulation within 10%.

Circuit techniques for a 1.8-V-only NAND flash memory

Focusing on internal high-voltage (V/sub pp/) switching and generation for low-voltage NAND flash memories, this paper describes a V/sub (pp)/ switch, row decoder, and charge-pump circuit. The proposed nMOS V/sub pp/ switch is composed of only intrinsic high-voltage transistors without channel implantation, which realizes both reduction of the minimum operating voltage and elimination of the V/sub pp/ leakage current. The proposed row decoder scheme is described in which all blocks are in selected state in standby so as to prevent standby current from flowing through the proposed V/sub pp/ switches in the row decoder. A merged charge-pump scheme generates a plurality of voltage levels with an individually optimized efficiency, which reduces circuit area in comparison with the conventional scheme that requires a separate charge-pump circuit for each voltage level. The proposed circuits were implemented on an experimental NAND flash memory. The charge pump and V/sub pp/ switch successfully operated at a supply voltage of 1.8 V with a standby current of 10 /spl mu/A. The proposed pump scheme reduced the area required for charge-pump circuits by 40%.

Fast and accurate programming method for multi-level NAND EEPROMs

For the replacement of conventional hard disks by NAND EEPROMs, a very high density and a high programming speed are required. An increased density can be achieved by using multi-level memory cells. With the new method, using staircase programming pulses combined with a bit-by-bit verify, a very narrow threshold voltage distribution of 0.7 V, necessary for 4-level or 2-bit operation, and a high programming speed of 300 /spl mu/s/page or 590 ns/byte can be obtained.

A double-level-V/sub th/ select gate array architecture for multilevel NAND flash memories

This paper first explains that gate array noise during a bit-by-bit program verify operation, named source line noise, is estimated to have a crucial adverse effect on the threshold voltage (V/sub th/) control and causes a serious problem in Multi-Level NAND Flash Memories. Then a new array architecture, a Double-Level-V/sub th/ Select Gate Array Architecture, is introduced to eliminate this noise without cell area penalty.

A 4 Mb NAND EEPROM with tight programmed V/sub t/ distribution

Described is a 5-V-only 4-Mb (512K*8 b) NAND EEPROM (electrically erasable programmable ROM) with tight programmed threshold voltage (V/sub t/) distribution, controlled by a novel program-verify technique. A tight programmed V/sub t/ distribution width of 0.8 V for the 4 Mb cell array is achieved. By introducing a compact row-decoder circuit, a die size of 7.28 mm*15.31 mm is achieved using 1.0 mu m design rules. A unique twin p-well structure has made it possible to realize low-power 5 V-only erase/program operation easily and to achieve 100 K-cycle endurance. >

A negative V/sub th/ cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories

A new, negative V/sub th/ cell architecture is proposed where both the erased and the programmed state have negative V/sub th/. This architecture realizes highly scalable, excellently noise-immune, and highly reliable NAND flash memories. The program disturbance that limits the scaling of a local oxidation of silicon (LOCOS) width in a conventional NAND-type cell is drastically reduced. As a result, the scaling limit of the LOCOS width decreases from 0.56 to 0.45 /spl mu/m, which leads to 20% isolation width reduction. The proposed cell is essential for the future scaled shallow trench isolated cells because improved program disturb characteristics can be obtained irrespective of the process technology or feature size. New circuit techniques, such as a PMOS drive column latch and a V/sub cc/-bit-line shield sensing method are also utilized to realize the proposed cell operation. By using these novel circuit technologies, array noise, such as a source-line noise and an inter bit line capacitive coupling noise, are eliminated. Consequently, the V/sub th/ fluctuation due to array noise is reduced from 0.7 to 0.1 V, and the V/sub th/ distribution width decreases from 1.2 to 0.6 V. In addition to the smaller cell size and the high noise immunity, the proposed cell improves device reliability. The read disturb time increases by more than three orders of magnitude, and a highly reliable operation can be realized.

Buried bit-line cell for 64 Mb DRAMs

The authors propose a buried bit-line (BBL) stacked capacitor cell structure for high-density dynamic random access memories (DRAMs). The cell area can be reduced to as small as 8.7<e1>F</e1>², where <e1>F</e1> is the lithographic feature size. A 2.25-&mu;m² cell area is achieved using a 0.51-&mu;m feature size. A 1.4-&mu;m² cell area is attainable using a 0.4-&mu;m feature size. The memory-cell vertical size (2<e1>F</e1>) includes a line and space for a trench isolation pattern in which the buried bit-line is formed. The horizontal size (4<e1>F</e1>+<e1>a</e1>) includes two word-line line and space pairs and a word-line to bit-line contact alignment tolerance denoted by <e1>a</e1>. A storage node contact is self-aligned to the word-line. Since the <e1>a</e1> is considered to be less than <e1>F</e1>/2, a cell area of less than 9<e1>F</e1>² is realized. If the bit-line contact is also self-aligned to the word-line, an 8<e1>F</e1>² cell area can in theory be realized

A multipage cell architecture for high-speed programming multilevel NAND flash memories

To realize low-cost, highly reliable, high-speed programming, and high-density multilevel flash memories, a multipage cell architecture has been proposed. This architecture enables both precise control of the V/sub th/ of a memory cell and fast programming without any area penalty. In the case of a four-level cell, a high programming speed of 236 /spl mu/s/512 bytes or 2.2 Mbytes/s can be obtained, which is 2.3 times faster than the conventional method. A small die size can be achieved with the newly developed compact four-level column latch circuit. A preferential page select method has also been proposed so as to improve the data retention characteristics. The IC error rate can be decreased by as much as 33%, and a highly reliable operation can be realized.

A high-density NAND EEPROM with block-page programming for microcomputer applications

A high-density, 5-V-only, 4-Mb CMOS EEPROM with a NAND-structured cell using Fowler-Nordheim tunneling for programming is discussed. The block-page mode is utilized for high-speed programming and easy microprocessor interface. On-chip test circuits for shortening test time and for evaluating cell characteristics yield highly reliable EEPROMs. The NAND EEPROM has many applications for microcomputer systems that require small size and large nonvolatile storage systems with low power consumption. >

A quick intelligent program architecture for 3 V-only NAND-EEPROMs

A quick program/program verify architecture with an intelligent verify circuit for 3-V-only NAND-EEPROMs is described. The verify circuit, which is composed of two transistors, provides a simple, intelligent program algorithm for 3-V-only operation. The total programming time is reduced to 50%. By using intelligent verify circuits, the memory cells which require more time to reach the program state are automatically detected. Verify-read, the modification of program data, and data reload are performed simultaneously. The chip size penalty is estimated to be only 1% for a 16-Mb NAND-EEPROM.<<ETX>>