Tomohiko Ohtsuka

Face focus coding under H.263+ video coding standard

In this paper, we present a new method to enhance image quality at face region of head and shoulder type image sequence and to shorten processing latency to achieve synchronization between lip movement and voice (lip sync). The new method can significantly improve image quality at face region and reduce frame skip operation during high movement image coding. Improvement is done by allocating more bits budget to the face region, where the centre of perceptual interest point usually located. Total number of bits of dynamically change background region is compressed by applying temporal filter to suppress background noise. We design a new fast rate control based on non-zero coefficient evaluation to shorten compression latency. The experimental result shows the increment of face regions PSNR by around 2 dB, the decreasing of skipping operation around 60 frames during encoding of 382 frames of highly movement video sequence and the advantage of having a very small compression latency around 3 frames which can resolve the lips sync problem.

A New Core and Delta Detection for Fingerprints Using the Extended Relation Graph

A new detection methodology for both of the core and the delta of the fingerprint using the extended relational graph is presented. This paper shows the way to detect both of the core loop and the delta loop from the extended relational graph, which we proposed in order to summarize the global feature of the fingerprint ridge pattern distribution. The experimental results for 180 fingerprint samples show that the processing time is ranging from 0.34 [sec] to 0.44 [sec] for each fingerprint image by using Pentium 4 1.8 GHz Processor. In our experiments, the core and the delta were successfully extracted in 94.4% of the 180 samples.

System-MSPA design of H.263+ video encoder LSI for face focused videotelephony

In this paper, an LSI design for video encoder and decoder for H.263+ video compression with object based coding is presented. LSI operates under clock frequency of 27 MHz to compress QCIF(176/spl times/144 pixels) at the frame rate of 30 PB-frame per second. The core size is 4.5/spl times/4.5 mm/sup 2/ in a 0.35 /spl mu/m process. The architecture is based on bus connected heterogeneous dedicated modules, named as system MSPA architecture. It employs fast and small-chip-area dedicated modules in lower level and controls them by employing the slow and flexible programmable device and an external DRAM. Design results achieve real time encoder in quite a compact size without losing flexibility and expandability. Real time emulation and easy test capability with external PC is also implemented.

Upper bounds for the degree of sequential diagnosability

It is known that an n-dimensional grid with N vertices, an N-vertex hypercube, and a k-ary tree with N vertices are sequentially /spl Omega/(N/sup n/(n+1)/)-, /spl Omega/(N log log N/log N)-, and /spl Omega/(/spl radic/N/k)-diagnosable, respectively. This paper shows that they are sequentially O(N/sup n/(n+1)/)-, O(N log log N//spl radic/log N)-, and o(/spl radic/kN)-diagnosable, respectively.

Translation of specifications in hierarchical analog LSI design

This paper proposes a novel approach for translation of specifications from system level to the next lower level. First, a prescribed response surface model is employed to approximate each output response y(x) over a region of interest /spl Omega/ of a vector of design variables x. The problem is to choose n distinct sampling points x/sub i/ (i=1,...,n) from /spl Omega/ at which observations y(x/sub i/) are to be taken. The data (y(x/sub i/), x/sub i/) are used to determine the parameter values of the response surface model. The derived response surface model and the constraints on the output responses are then transformed into interval-inequality-constrained optimization problem. Interval methods consist a set of procedures for interval arithmetics. They provide solutions for the optimization problem in form of hyperbox space of design variables. This hyperbox is suitable for independent translation of specifications from system level to the next lower level. Our approach successfully applies to analog PLL design.

Hierarchical circuit optimization for analog LSIs using device model refining

This paper presents a new approach to circuit optimization, aiming at both short optimization time and high accuracy. Initially, the design variables of the analog circuit module are optimized with simple transistor models with the aim at making design variables closer to the optimal solution speedy. After the design variable vector reaches the near optimal solution, the device model refinement is performed for each device to achieve higher precision. This procedure is repeated until the device model becomes precise enough in the IC environment. The sequence of the device model refinement should be set in advance by designers. A design example indicates that the optimization using device model refining can be carried out in a shorter time than the simulation based approach, whilst achieving a high precision for the solution.