Tomoyasu Inoue

A New MOS Process Using MoSi2 as a Gate Material

MoSi2 film properties for a gate material in LSI were investigated. The film resistivity was 7×10-4 ohm-cm and decreased to 1×10-4 ohm-cm after annealing at high temperature. The structure was amorphous in as-deposited film and changed to polycrystalline with nearly 500 A grains after annealing. The film oxidation rate was as low as that of poly Si, because of SiO2 formation on the film surface. The properties against chemical reagents used in LSI process were similar to those of poly Si. MoSi2 gate MOS device characteristics were investigated. A high speed ROM was fabricated with MoSi2 for gate material.

Improvement of SOS Device Performance by Solid-Phase Epitaxy

Crystalline quality in the whole region of silicon film on sapphire substrate has been improved by doubly applying solid-phase epitaxial regrowth combined with amorphization of both the silicon surface and the silicon-sapphire interface regions of SOS. Observations, by Rutherford backscattering and chemical delineation, indicate that planar defect density in the film becomes less than 1/100 of that in an as-grown film. Effective mobilities of n- and p-channel FETs in the improved film are 520 and 225 cm2/Vs, which are 1.3 times and 1.1 times larger than those in the as-grown film, respectively. A significantly reduced drain leakage current of 1.8×1012 A/50 µm for n-channel FET is obtained, whose value is about 1/100 of those in as-grown samples. The higher mobility and lower leakage current thus obtained, should be attributed to the drastic improvement of crystalline quality in the whole region of SOS by the double solid-phase epitaxy.

Crystalline disorder reduction and defect‐type change in silicon on sapphire films by silicon implantation and subsequent thermal annealing

Ion channeling techniques have been utilized to study the improvement of crystalline quality of SOS films by Si implantation and subsequent thermal annealing. Crystalline disorder was greatly reduced when an amorphous layer was formed at the Si/sapphire interface and annealed at temperatures higher than 600 °C. It was shown that the regrowth of the amorphous layer proceeded from the surface toward the inner region. In the 200–400‐keV proton channeling measurements, the dechanneled fraction was found to be proportional to the square root of the proton energy in the crystalline improved SOS, whereas as‐grown SOS had no energy dependence. This indicates a defect‐type change from microtwins to dislocations during the above treatment.

Intermediate Amorphous Layer Formation Mechanism at the Interface of Epitaxial CeO2 Layers and Si Substrates

The formation mechanism of an intermediate amorphous layer between epitaxially grown CeO2 layers and silicon substrates is studied using cross-sectional transmission electron microscopy and Auger electron spectroscopy. The intermediate amorphous layer thickness increases after annealing at 800°C in air, whereas it decreases somewhat after annealing in an ultrahigh vacuum. Auger in-depth analysis verifies that the intermediate amorphous layer is silicon dioxide. The intermediate oxide growth of the CeO2/Si structures due to intentional oxidation at 700~900°C in a dry oxygen ambient is analyzed and the results indicate that the oxidation proceeds in an intermediate step between reaction limited and diffusion limited processes. The intermediate amorphous layer formation mechanism is concluded to be oxygen diffusion through CeO2 layers and successive oxidation of silicon at the interface.

Oxidation of sputtered molybdenum silicide thin films

An Auger in‐depth analysis and a 350 keV He+ backscattering technique were used to investigate the growth of an SiO2 protective layer and the compositional change in sputtered molybdenum silicide films after oxidation, respectively. Silicon depletion and molybdenum pileup in molybdenum silicide were observed near the SiO2/Mo‐Si interface. The film becomes molybdenum rich with increasing oxidation time. The Si/Mo atomic ratio decreases rapidly in the first 30‐min period and then decreases slowly, nearly proportionally to the square root of the oxidation time. These behaviors are explained by the preferential oxidation of silicon and the reduced silicon present at the SiO2/Mo‐Si interface from the rest of the molybdenum silicide layer.

Electron-beam-assisted evaporation of epitaxial CeO2 thin films on Si substrates

Electron-beam-assisted evaporation is a way to lower the growth temperature and improve crystalline quality of CeO2(110) layers on Si(100) substrates. The electron-beam-assisted evaporation system is constructed utilizing an electron-beam-irradiation system with a suppressor electrode around the sample holder. The suppressor bias condition is optimized as a function of acceleration energy of assisting electrons. The epitaxial growth quality depends on the assisting electron-beam energy. Optimum electron energy is experimentally determined to be around 360 eV, wherein the epitaxial temperature is lowered to 710 °C, i.e., temperature lowering of more than 100 °C compared with the conventional growth method.

Highly controllable pseudoline electron-beam recrystallization of silicon on insulator

A new electron‐beam annealing technique, an amplitude modulated pseudoline electron beam, has been proposed for recrystallization of large‐area silicon layers on insulating materials (SOI). The technique utilizes an amplitude modulated sinusoidal wave for high‐frequency beam oscillation. Through computer simulation of the temperature distribution for the sample surface, precise control of the position probability density profile of the line beam proved to be essential in realizing wide and uniform annealing. An optimum oscillation waveform was determined from the simulation. A large‐area SOI, 4 mm ⧠, was successfully recrystallized.

Crystalline quality improvement of SOS films by SI implantation and subsequent annealing

Abstract Crystalline defects in SOS films have been reduced significantly by solid phase epitaxial regrowth after amorphizing the SOS in the vicinity of the silicon-sapphire interface. Amorphization was performed by random implantation of silicon ions. The optimum implantation was chosen to give a projected range of silicon ions and a surface crystalline layer ≈0.8 and 0.2–0.3 times the SOS thickness, respectively. The regrowth proceeds during thermal annealing at more than 600°C. Higher temperature annealing leads to a more drastic defect reduction. Dechanneling energy dependence measurements in 250–400 keV 3 He ion axial channeling were applied to defect structure analysis as a function of depth, and revealed that defect-type changed from twins and/or stacking faults to dislocations and that the dislocation density decreased with depth after the regrowth.

Grain growth of polycrystalline silicon films on SiO2 by cw scanning electron beam annealing

Reduced pressure, chemical vapor deposited polycrystalline silicon films (5000 A thick) over thermally grown SiO2 on (100) silicon wafers are recrystallized by a scanning electron microscope modified electron beam annealing system. On the basis of transmission electron microscope bright‐field images and electron diffraction patterns, large grained polycrystalline silicon films of 20‐μm average grain size are obtained after electron beam annealing. Electron beam current, scanning rate, and annealing repetition are found to be important parameters in the recrystallization. Optimum values for them are from 1.6 to 1.9 mA, from 40 to 80 cm/sec, and from 5 to 10 times, respectively.

Seeding lateral epitaxy of silicon on insulator with improved seed and cap structure by pseudoline shaped electron beam annealing

Seeding lateral epitaxy for silicon films on an insulator, using pseudoline shaped electron beam annealing, has been investigated. Higher oscillation frequency, higher beam scanning velocity, and suitable oscillation amplitude were effective to achieve large uniform silicon on insulator (SOI) films with the aid of simulating temperature distribution in silicon substrate. Furthermore, improved seed with tapered edge and capping layer of tungsten/insulator were employed to obtain 300 μm×1.3 mm single‐crystal SOI films on a 1.3‐μm SiO2 layer. Stacked SOI devices were successfully fabricated with low‐temperature planarization process. 218 ps/stage propagation delay and 17 pJ power‐delay product were obtained.