Hiroyuki Tango

On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration

This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFETs degraded by Fowler-Nordheim electron injection. >

On the universality of inversion layer mobility in Si MOSFET's: Part II-effects of surface orientation

For part I see ibid., vol.41, no.12, pp.2357-62 (1994). This paper reports the studies of the inversion layer mobilities in n-channel MOSFETs fabricated on Si wafers with three surface orientations ([100], [110], and [111]) from the viewpoint of the universal relationship against the effective field, E/sub eff/(=q(N/sub dpl/+/spl eta//spl middot/N/sub s/)//spl epsi/Si). It is found that the universality does hold for the electron mobilities on [110] and [111], when the value of /spl eta/ is taken to be 1/3, different from the electron mobility on [100], where /spl eta/ is 1/2. Also, the E/sub eff/ dependence of the electron mobility is found to differ among [100], [110], and [111] surfaces. This is attributed to the differences in the E/sub eff/ dependence of the mobility limited by surface roughness scattering among the orientations. The origins of E/sub eff/ and /spl eta/ are discussed on the basis of the relaxation time approximation for a 2DEG (2-dimensional electron gas). While the surface orientation dependence of /spl eta/ in phonon scattering can be understood in terms of the subband occupation, it is found that the theoretical formulation of surface roughness scattering, used currently, needs to be refined in order to explain the differences in E/sub eff/ dependence and the value of /spl eta/ among the three orientations. >

Two-dimensional simulation and measurement of high-performance MOSFETs made on a very thin SOI film

Thinning effects on the device characteristics of silicon-on-insulator (SOI) MOSFETs are discussed. Two-dimensional/two-carrier device simulation revealed the following advantages. An n-channel MOSFET with 500-AA-SOI thickness exhibited a high-punchthrough resistance as well as an improved subthreshold swing down to a deep submicrometer region, even if the film was nearly intrinsic. A capacitance coupling model has been proposed to explain these subthreshold characteristics. The kink elimination effect, which was attributed to a significantly reduced hole density in the SOI film, was reproduced. The low-field channel mobility exhibited a significant increase, which was ascribed to a decrease in the vertical electric field. Moreover, the current-overshoot phenomenon associated with the switching operation was suppressed. Excess holes recombine with electrons quickly after the gate turn-on, bringing about a stabilized potential in the SOI substrate. Experiments were also carried out to verify the simulation. >

Improvement of SOS Device Performance by Solid-Phase Epitaxy

Crystalline quality in the whole region of silicon film on sapphire substrate has been improved by doubly applying solid-phase epitaxial regrowth combined with amorphization of both the silicon surface and the silicon-sapphire interface regions of SOS. Observations, by Rutherford backscattering and chemical delineation, indicate that planar defect density in the film becomes less than 1/100 of that in an as-grown film. Effective mobilities of n- and p-channel FETs in the improved film are 520 and 225 cm2/Vs, which are 1.3 times and 1.1 times larger than those in the as-grown film, respectively. A significantly reduced drain leakage current of 1.8×1012 A/50 µm for n-channel FET is obtained, whose value is about 1/100 of those in as-grown samples. The higher mobility and lower leakage current thus obtained, should be attributed to the drastic improvement of crystalline quality in the whole region of SOS by the double solid-phase epitaxy.

Suppression of the floating-body effect in SOI MOSFET's by the bandgap engineering method using a Si/sub 1-x/Ge/sub x/ source structure

The bandgap engineering method using a SiGe source structure is presented as a means to suppress the floating-body effect in SOI MOSFETs. Experiments using Ge implantation are carried out to form a narrow-bandgapped SiGe layer in the source region. It has been confirmed that Ge-implanted SIMOX exhibited a 0.1 eV bandgap narrowing with a relatively low Ge-dosage of 10/sup 16/ cm/sup -2/. The fabricated N-type SOI-MOSFETs exhibited suppressed parasitic bipolar effects, such as improvement of the drain breakdown voltage or latch voltage, and suppression of abnormal subthreshold slope. Advantages over other conventional methods are also discussed, indicating that the bandgap engineering provides a practical method to suppress the floating-body effect.

Three-dimensional analysis of subthreshold swing and transconductance for fully-recessed-oxide (trench) isolated 1/4- mu m-width MOSFETs

The dependence of MOSFET gate controllability on the field-isolation scheme is investigated using three-dimensional simulation. It is found that a fully-recessed-oxide (trench) isolated MOSFET has a steep subthreshold characteristic and high transconductance in comparison with a nonrecessed device. These features result from the small depletion capacitance due to the crowding of the gates fringing field at the channel edge. It is also found that the gate and diffused line capacitances in the case of fully-recessed-oxide isolation are small, so that high switching speed operation can be expected. These features are enhanced with a reduction in the channel width, especially for lower-submicrometer-width MOSFETs. A drawback of a fully-recessed-oxide MOSFETs is its low threshold voltage. However, the leakage current is not as large as that inferred from the inverse narrow-channel effect because of its steep subthreshold characteristic. Several countermeasures for this low threshold voltage are discussed. >

Standby/active mode logic for sub-1-V operating ULSI memory

New gate logics, standby/active mode logic I and II, for future 1 Gb/4 Gb DRAMs and battery operated memories are proposed. The circuits realize sub-l-V supply voltage operation with a small 1-/spl mu/A standby subthreshold leakage current, by allowing 1 mA leakage in the active cycle. Logic I is composed of logic gates using dual threshold voltage (Vt) transistors, and it can achieve low standby leakage by adopting high Vt transistors only to transistors which cause a standby leakage current. Logic II uses dual supply voltage lines, and reduces the standby leakage by controlling the supply voltage of transistors dissipating a standby leakage current. The gate delay of logic I is reduced by 30-37% at the supply voltage of 1.5-1.0 V, and the gate delay of logic II is reduced by 40-85% at the supply voltage of 1.5-0.8 V, as compared to that of the conventional CMOS logic. >

High aspect ratio hole filling by tungsten chemical vapor deposition combined with a silicon sidewall and barrier metal for multilevel interconnection

A newly developed processing for high aspect ratio hole filling by tungsten chemical vapor deposition, combined with a Si sidewall technique and resist etch back is proposed. A high aspect ratio hole (around 3) was completely filled with W and W‐Si alloy without voids. It is also proposed to interpose a TiN/TiSi2 layer between W and Si, in order to suppress rapid silicidation of W at high temperatures above 800 °C. Silicidation rates for W/TiN/TiSi2/Si systems were 2–2.5 orders of magnitude lower than W/Si systems. Electrical contact resistivity was kept to be lower than 1×10−5 Ω cm2 even after 900 °C annealing by suppressing rapid silicidation of W.

High performance SOIMOSFET using ultra-thin SOI film

Advantages of using an ultra-thin SOI substrate for SOIMOSFET are discussed using a 2- carrier/2-dimensional simulation. Ultra-thin SOIMOSFET has been shown to possess sharp subthreshold slope and high punchthrough resistance nearly independent of doping concentration. Low field mobility in ultra-thin SOIMOSFET has been predicted to increase up to approximately the maximum value which is obtainable in the inversion layer. The disappearance of kink associated with thinning the SOI film has been reproduced in the simulation. Moreover, it has been found that the current overshoot is virtually suppressed in thin-SOI MOSFET, enabling one to obtain a stable current irrespective of pulse intervals. These results bring SOIMOSFETs an anticipation as a promising alternative for bulk MOSFETs in the application of high speed and small-featured devices.

An 18 ns CMOS/SOS 4K static RAM

A high-speed CMOS/SOS 4K word/spl times/1 bit static RAM is described. The RAM features a MoSi/SUB 2/ gate CMOS/SOS technology with 2 /spl mu/m gate length and 500 /spl Aring/ thick gate oxide. Performance advantage of SOS over bulk is discussed for the scaled-down MOS LSI with 1-2 /spl mu/m gate. A standard 6-transistor CMOS cell and a two-stage sense amplifier scheme are utilized. In spite of the rather conservative 3.5 /spl mu/m design rule except for the 2 /spl mu/m gate length, the cell size of 36/spl times/36 /spl mu/m, the die size of 3.11/spl times/4.07 mm, and the typical read access and cycle time of 18 ns are achieved. The active and standby power dissipation are 200 mW and 50 /spl mu/W, respectively.