T. Yoshii

Improvement of SOS Device Performance by Solid-Phase Epitaxy

Crystalline quality in the whole region of silicon film on sapphire substrate has been improved by doubly applying solid-phase epitaxial regrowth combined with amorphization of both the silicon surface and the silicon-sapphire interface regions of SOS. Observations, by Rutherford backscattering and chemical delineation, indicate that planar defect density in the film becomes less than 1/100 of that in an as-grown film. Effective mobilities of n- and p-channel FETs in the improved film are 520 and 225 cm2/Vs, which are 1.3 times and 1.1 times larger than those in the as-grown film, respectively. A significantly reduced drain leakage current of 1.8×1012 A/50 µm for n-channel FET is obtained, whose value is about 1/100 of those in as-grown samples. The higher mobility and lower leakage current thus obtained, should be attributed to the drastic improvement of crystalline quality in the whole region of SOS by the double solid-phase epitaxy.

Crystalline disorder reduction and defect‐type change in silicon on sapphire films by silicon implantation and subsequent thermal annealing

Ion channeling techniques have been utilized to study the improvement of crystalline quality of SOS films by Si implantation and subsequent thermal annealing. Crystalline disorder was greatly reduced when an amorphous layer was formed at the Si/sapphire interface and annealed at temperatures higher than 600 °C. It was shown that the regrowth of the amorphous layer proceeded from the surface toward the inner region. In the 200–400‐keV proton channeling measurements, the dechanneled fraction was found to be proportional to the square root of the proton energy in the crystalline improved SOS, whereas as‐grown SOS had no energy dependence. This indicates a defect‐type change from microtwins to dislocations during the above treatment.

High aspect ratio hole filling by tungsten chemical vapor deposition combined with a silicon sidewall and barrier metal for multilevel interconnection

A newly developed processing for high aspect ratio hole filling by tungsten chemical vapor deposition, combined with a Si sidewall technique and resist etch back is proposed. A high aspect ratio hole (around 3) was completely filled with W and W‐Si alloy without voids. It is also proposed to interpose a TiN/TiSi2 layer between W and Si, in order to suppress rapid silicidation of W at high temperatures above 800 °C. Silicidation rates for W/TiN/TiSi2/Si systems were 2–2.5 orders of magnitude lower than W/Si systems. Electrical contact resistivity was kept to be lower than 1×10−5 Ω cm2 even after 900 °C annealing by suppressing rapid silicidation of W.

Highly controllable pseudoline electron-beam recrystallization of silicon on insulator

A new electron‐beam annealing technique, an amplitude modulated pseudoline electron beam, has been proposed for recrystallization of large‐area silicon layers on insulating materials (SOI). The technique utilizes an amplitude modulated sinusoidal wave for high‐frequency beam oscillation. Through computer simulation of the temperature distribution for the sample surface, precise control of the position probability density profile of the line beam proved to be essential in realizing wide and uniform annealing. An optimum oscillation waveform was determined from the simulation. A large‐area SOI, 4 mm ⧠, was successfully recrystallized.

Crystalline quality improvement of SOS films by SI implantation and subsequent annealing

Abstract Crystalline defects in SOS films have been reduced significantly by solid phase epitaxial regrowth after amorphizing the SOS in the vicinity of the silicon-sapphire interface. Amorphization was performed by random implantation of silicon ions. The optimum implantation was chosen to give a projected range of silicon ions and a surface crystalline layer ≈0.8 and 0.2–0.3 times the SOS thickness, respectively. The regrowth proceeds during thermal annealing at more than 600°C. Higher temperature annealing leads to a more drastic defect reduction. Dechanneling energy dependence measurements in 250–400 keV 3 He ion axial channeling were applied to defect structure analysis as a function of depth, and revealed that defect-type changed from twins and/or stacking faults to dislocations and that the dislocation density decreased with depth after the regrowth.

Seeding lateral epitaxy of silicon on insulator with improved seed and cap structure by pseudoline shaped electron beam annealing

Seeding lateral epitaxy for silicon films on an insulator, using pseudoline shaped electron beam annealing, has been investigated. Higher oscillation frequency, higher beam scanning velocity, and suitable oscillation amplitude were effective to achieve large uniform silicon on insulator (SOI) films with the aid of simulating temperature distribution in silicon substrate. Furthermore, improved seed with tapered edge and capping layer of tungsten/insulator were employed to obtain 300 μm×1.3 mm single‐crystal SOI films on a 1.3‐μm SiO2 layer. Stacked SOI devices were successfully fabricated with low‐temperature planarization process. 218 ps/stage propagation delay and 17 pJ power‐delay product were obtained.

Application of E-beam recrystallization to three-layer image processor fabrication

E-beam recrystallization has been applied to the fabrication of a three-layer processor. The seed structure and the E-beam conditions were successfully optimized so that a large-area SOI as wide as 1 mm was recrystallized without void generation with no damage to underlying devices. The actual SOI area in the device, 850*1100 mu m, was recrystallized with one E-beam scan by aligning its position. The three-layer image processor was capable of visual image sensing with a feature outline extraction in a parallel processing manner. Normal operations of the fundamental functions have been confirmed, demonstrating the feasibility of E-beam recrystallization for three-dimensional IC application. >

Effect of interfacial oxide on solid-phase epitaxy of Si films deposited on Si substrates

The effect of interfacial oxide on defect generation and regrowth rate in solid‐phase epitaxy of amorphized Si has been investigated. Si‐ion implantation was used to amorphize the chemical‐vapor‐deposited polycrystalline Si (poly‐Si) and to reduce the oxygen concentration at the poly/single‐crystalline Si interface. The crystallinity of the epitaxial layers obtained under different conditions, such as surface treatment, Si‐ion‐implantation dose, and thermal annealing, was examined by high‐resolution electron microscopy and Rutherford backscattering spectroscopy (RBS). Experimental results showed that microtwins were induced by inhomogenious oxygen distribution at the interface and that low defect density (the channeling minimum yield in RBS; χmin=7%) could be achieved for specimens with maximum interfacial oxide thickness of about 4 A.

Multilevel construction of seeded‐laterally epitaxial silicon films on insulator

A new seed structure, partially thickened silicon films on insulator (PTS), is proposed for multilevel seeded‐laterally epitaxial silicon films on insulator (SOI). Two‐level seeded‐laterally epitaxial silicon films on thick SiO2 (2.5 μm) were successfully fabricated, using the PTS structure in conjunction with the electron‐beam technique. The SOI surface flatness after recrystallization was also improved by the PTS. Through computer simulation of the electron‐beam recrystallization process, it is determined that the PTS structure enhances the lateral heat conduction within the SOI. This is important in smoothly melting the seed and field SOI regions.

Barrier metal between tungsten and silicon for high temperature processing

Abstract The reaction scheme in W/TiN/TiSi2/Si(100) and W/TiN/Si(100) systems was studied by Rutherford backscattering spectroscopy. By using the TiN/TiSi2 and TiN diffusion barrier layers, the tungsten silicidation rate is reduced by 2 and 4.5 orders of magnitude, respectively, compared with the silicidation rate of the W/Si system. Considering the activation energy of the WSi2 formation, the reaction rate for the W/TiN/TiSi2/Si system is found to be controlled by the Si supply at the W/TiN interface. Si is supplied from the Si substrate through the TiN/TiSi2 layer to the W/TiN interface. The rate-limiting process is considered to be the Si bond breaking at the TiSi2/Si interface. TiN films with 10 nm thickness are thick enough to suppress reactions and maintain adhesion even after annealing at 950°C for 5 h.