Tomoyuki Someya

Normally-off SiC-JFET inverter with low-voltage control and a high-speed drive circuit

A highly efficient inverter was achieved by using normally-off SiC-JFETs (silicon carbide junction FETs) as switching devices. A precise control system for the gate voltage and the high-speed driver circuit are quite important issues in the realization of an inverter system for operating JFETs with threshold voltage lower than 2V and for the reduction of switching loss. A two step push-pull circuit for precise control of the gate voltage and a speed-up capacitor circuit for high-speed operation are developed and high-speed switching of 600 V/2A SiC-JFET modules is demonstrated. The 50 W fan motor for an exterior unit of an air conditioner has been successfully operated by these SiC modules and developed driver circuits, and the the inverter efficiency was improved by about 6%, compared with conventional IGBT inverters.

Normally-Off 4H-SiC Vertical JFET with Large Current Density

We developed normally-off 4H-SiC vertical junction field effect transistors (JFETs) with large current density. The effect of forming an abrupt junction between the gate and the channel was simulated, and vertical JFETs were then fabricated with abrupt junctions. As a result, a large rated drain current density (500 A/cm2) and a low specific on-resistance (2.0 mWcm2) were achieved for small devices. The blocking voltage was 600 V. These results were due to a reduction of the threshold voltage by forming the abrupt junction between the gate and the channel.

A novel CMOS-compatible lateral bipolar transistor for high-speed BiCMOS LSI

A CMOS-compatible lateral bipolar transistor suitable for low-cost and high-speed BiCMOS LSIs is proposed, and its high-speed characteristics are demonstrated. The proposed lateral bipolar transistor has a structure analogous to NMOS transistors, which use a source and drain self-aligned structure to form an emitter and collector. The obtained values of h/sub FE/, BV/sub CEO/, R/sub CS/, f/sub TMAX/, and r/sub bb/, are 20, 7 V, 50 Omega , 6.3 GHz, and 450 Omega , respectively. Moreover, delay times of a two-input NAND BiCMOS gate circuit are 0.28 ns when unloaded, and 0.42 ns and 0.53 ns when load capacitances are 1 pF and 2 pF, respectively. These values are equal to those of conventional poly-Si emitter bipolar transistors.<<ETX>>

Design consideration for 2 kV SiC-SIT

Process technologies of the novel Static Induction transistor with source-gate self-aligned and overlapping (SAO) structures are considered in order to reduce the restrictions of alignment problems. A SiC-SIT with SAO structure is fabricated by using aluminum implantation for p gate on 4H n-type SiC. It is found that the SAO structure can be fabricated as expected by observing the cross sectional structure. Very low specific on-resistance of 39 m/spl Omega/ cm/sup 2/ is successfully obtained. By reducing a unit cell, lower on-resistance can be expected as a half of this work.

Switching properties of 2 kV SiC-SIT

A completely vertical channel type static induction transistor with the novel gate structure is fabricated. Highest blocking voltage of 2000 V in the case of vertical channel type silicon carbide SITs and low on-resistance of 70 m/spl Omega//spl middot/cm/sup 2/ are realized. Turn-off characteristics are investigated and very fast turn-off time of 20 ns at high temperature of 200/spl deg/C under dc voltage of 1000 V is successfully demonstrated. Large current turned-off properties are also demonstrated by a parallel connection of two small SITs.