Tony Lin

A Novel Shallow Trench Isolation with Mini-Spacer Technology

A new shallow trench isolation (STI) process with a mini-spacer at the masking nitride sidewall before silicon trench etching was proposed. With this mini-spacer, thicker corner liner oxide and a T-shaped trench oxide can be formed simultaneously. The issue of oxide-recess at STI corner can be effectively reduced and larger process window for subthreshold kink free device were obtained. The isolation capability and junction integrity were both improved as compared with those of the conventional STI process. Reverse narrow width effect as well as gate oxide integrity were also improved. This technology was employed for 0.13 µm complementary metal oxide silicon (CMOS) device fabrication.

The effects of super-steep-retrograde indium channel profile on deep submicron n-channel metal-oxide-semiconductor field-effect transistor

A complete study on the effects of indium channel implant energy on transistor characteristics including carrier mobility, drain current, drain induce barrier lowering (DIBL), device breakdown, junction leakage, impact ionization rate and hot-carrier degradation were performed on 0.1 µm devices. It was found that devices with super-steep-retrograde (SSR) indium channel profile depict higher transconductance in linear region, albeit the saturation drive current is lower, compared to the conventional BF2-doped control. In addition, In-doped devices also depict improved DIBL, Ion–Ioff current ratio and transistor breakdown voltage. Finally, by increasing the indium implant energy, devices depict an improved transconductance, reduced DIBL and hot-carrier degradation, while suffering larger junction leakage and capacitance.

Effect of STI Stress Enhanced Boron Diffusion on Leakage and Vcc_min of Sub-65nm node Low-Power SRAM

A new finding and explanation of STI stress enhanced sidewall boron dopant diffusion effect on BTBT and Vcc_min of 65nm node low-power SRAM is presented. A significant increase of BTBT on STI edge sidewall was observed with non-optimized STI process, which suffers more seriously LOD effect. The defect enhanced boron diffusion model integrated the STI stress effect on defect generation is used to explain this observation. The BTBT degradation is attributed to the STI sidewall boron dopant enhanced diffusion and increased junction electric field of STI sidewall. This boron diffusion is random and more seriously in SRAM cell, thus results in worse pass-gate device mismatch and Vcc_min of 65nm node SRAM.

Optimization of Active Geometry Configuration and Shallow Trench Isolation (STI) Stress for Advanced CMOS Devices

Mechanical stress induced by active geometry is optimized for minimum variation of complementary metal oxide semiconductor (CMOS) electrical characteristics with varying active profiles. In this study, wafers with two different shallow trench isolation (STI) stress levels were investigated. By co-optimizing the active profile and STI stress level of model test structures, less than 3% device deviation is achieved when compared with simulation program with integrated circuit emphasis (SPICE) model in the full breadth of N channel and P channel metal oxide semiconductor (N/PMOS) geometry.

Optimization of STI Stress and Active Geometry Configuration for Advanced CMOS Devices

Abstract Active geometry induced mechanical stress is optimized for minimum variation of CMOS electrical characteristics with varying active profiles. Wafers with two different STI stress levels were manufactured for this study. By co-optimizing STI stress and the active profile of model test structures, less than 3% device deviation was achieved in comparison to SPICE model across the full breadth of N/PMOS geometry.