Coming Chen

Silicon integrated high performance inductors in a 0.18 /spl mu/m CMOS technology for MMIC

This paper presents a complete portfolio of silicon integrated inductors in a 0.18 μm CMOS technology. In addition to inductor design, we also present a complete optimization methodology with associated modeling and key characterization. Our inductor quality factors have been enhanced by optimizing patterned ground shield and taper coils or using copper metallization. The quality-factor peak can further be optimized at an application-specific frequency band with our optimization algorithm. To facilitate IC design with inductors, a novel model considering eddy current loss was developed, Finally, to integrate inductors into a system-chip, inductor-to-inductor and substrate-inductor coupling were investigated.

high-performance and high-reliability 80-nm gate-length DTMOS with indium super steep retrograde channel

In this paper, we demonstrate for the first time a high-performance and high-reliability 80-nm gate-length dynamic threshold voltage MOSFET (DTMOS) using indium super steep retrograde channel implantation. Due to the steep indium super steep retrograde (In SSR) dopant profile in the channel depletion region, the novel In-SSR DTMOS features a low V/sub th/ in the off-state suitable for low-voltage operation and a large body effect to fully exploit the DTMOS advantage simultaneously, which is not possible with conventional DTMOS. As a result, excellent 80-nm gate length transistor characteristics with drive current as high as 348 /spl mu/A//spl mu/m (off-state current 40 nA//spl mu/m), a record-high Gm=1022 mS/mm, and a subthreshold slope of 74 mV/dec, are achieved at 0.7 V operation. Moreover, the reduced body effects that have seriously undermined conventional DTMOS operation in narrow-width devices are alleviated in the In-SSR DTMOS, due to reduced indium dopant segregation. Finally, it was found for the first time that hot-carrier reliability is also improved in DTMOS-mode operation, especially for In-SSR DTMOS.

A Novel Shallow Trench Isolation with Mini-Spacer Technology

A new shallow trench isolation (STI) process with a mini-spacer at the masking nitride sidewall before silicon trench etching was proposed. With this mini-spacer, thicker corner liner oxide and a T-shaped trench oxide can be formed simultaneously. The issue of oxide-recess at STI corner can be effectively reduced and larger process window for subthreshold kink free device were obtained. The isolation capability and junction integrity were both improved as compared with those of the conventional STI process. Reverse narrow width effect as well as gate oxide integrity were also improved. This technology was employed for 0.13 µm complementary metal oxide silicon (CMOS) device fabrication.

An anomalous crossover in Vth roll-off for indium-doped nMOSFETs

The effects of indium channel implant energy on short-channel effect (SCE) and narrow channel effect (NCE) were studied on NMOS devices down to 0.1 /spl mu/m channel length. An anomalous crossover in Vth roll-off curves was observed, for the first time, on indium-implanted splits with different implant energies. This intriguing finding, together with the observed reduction in reverse narrow channel effect (RNCE) and effective channel length with reducing indium implant energy, can be consistently explained by the suppression of transient enhanced diffusion (TED) of channel impurity due to indium deactivation.

A Modified Capacitance–Voltage Method Used for Leff Extraction and Process Monitoring in Advanced 0.15 µm Complementary Metal-Oxide-Semiconductor Technology and Beyond

In this paper, an alternative approach for the extraction of effective channel length, Leff, using a modified capacitance–voltage (C–V) method [the capacitance–ratio (C–R) method], which considers depletion effect compensation is proposed. In general, we define Leff=Lmask-ΔL, where ΔL is the sum of the polysilicon gate lithography bias and two times the overlap length of the polysilicon gate and source/drain (S/D) extension (ΔL=Lpb+2Lovlap). Using the modified C–V method, more consistent and reasonable Leff data can be extracted as compared to those obtained using the newest current–voltage (I–V) method (shift and ratio method). In using the proposed C–R method, we can electrically measure the exact Lpb and Lovlap numbers that can both be used as process monitor parameters. The within-wafer uniformities of Leff (or ΔL), Lpb and Lovlap have also been checked among devices of various sizes. After the Leff is extracted, a stable S/D resistance Rsd, with Vg independence, is determined and verified using the I–V method. The parasitic capacitance Cgd is another extracted parameter that is as important as Rsd in SPICE modeling for RF complementary metal-oxide-semiconductor (CMOS) applications.

The effects of super-steep-retrograde indium channel profile on deep submicron n-channel metal-oxide-semiconductor field-effect transistor

A complete study on the effects of indium channel implant energy on transistor characteristics including carrier mobility, drain current, drain induce barrier lowering (DIBL), device breakdown, junction leakage, impact ionization rate and hot-carrier degradation were performed on 0.1 µm devices. It was found that devices with super-steep-retrograde (SSR) indium channel profile depict higher transconductance in linear region, albeit the saturation drive current is lower, compared to the conventional BF2-doped control. In addition, In-doped devices also depict improved DIBL, Ion–Ioff current ratio and transistor breakdown voltage. Finally, by increasing the indium implant energy, devices depict an improved transconductance, reduced DIBL and hot-carrier degradation, while suffering larger junction leakage and capacitance.

Shallow-trench isolation with raised-field-oxide structure

This paper describes a novel shallow-trench isolation (STI) structure to suppress the corner metal-oxide semiconductor field-effect transistor (MOSFET) inherent to trench isolation. A gate oxide and a thin polysilicon layer are first processed, and are then followed by the STI process. With this raised-field-oxide structure, the anomalous subthreshold conduction of the shallow-trench isolated MOSFETs due to electric-field crowding at the active edge has been successfully eliminated. No inverse-narrow-width effect is observed as the device width has been scaled down to 0.3 µm. The raised-field-oxide structure provides a larger process margin for planarization, and good device characteristics were achieved by this novel STI structure.

Optimization of short channel effect with arsenic halo implant through polysilicon gate

Excellent p-type metal oxide semiconductor (PMOS) short channel effect is achieved by using a high-energy, large tilt angle arsenic implant as a P-channel halo. For the first time, it was found that the dopant profile of Halo was implanted through the poly-silicon gate. The channel concentration is modulated not only laterally from the gate edge but also vertically from the top of the polysilicon gate and this resulted in very flat short channel behavior. The effect of the arsenic halo implant was comprehensively studied and well characterized to explain this specific phenomenon. The gate-oxide integrity was examined by charge to break down (QBD). Excellent performance of 0.12 µm PMOSFET is also demonstrated in this work.