Toru Anezaki
Fujitsu
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Publication
Featured researches published by Toru Anezaki.
international solid-state circuits conference | 1997
Atsushi Hatakeyama; Hirohiko Mochizuki; Tadao Aikawa; Masato Takita; Yuki Ishii; Hironobu Tsuboi; Shinya Fujioka; Shusaku Yamaguchi; Makoto Koga; Yuji Serizawa; Koichi Nishimura; Kuninori Kawabata; Yoshinori Okajima; Michiari Kawano; Hideyuki Kojima; Kazuhiro Mizutani; Toru Anezaki; Masatomo Hasegawa; Masao Taguchi
This 256 Mb synchronous DRAM with 1 ns clock access is stable against temperature, voltage, and process variation by use of an innovative register-controlled delay locked loop (RDLL). Unlike most conventional high-density DRAMs, the bit-lines are placed above the storage capacitors in this DRAM to relax design rules of the core area. The noise issues are analyzed and resolved to help implement the technology in mass production of 0.28 to 0.24 /spl mu/m 200 MHz DRAMs.
Archive | 2005
Taiji Ema; Hideyuki Kojima; Toru Anezaki
Archive | 2005
Taiji Ema; Hideyuki Kojima; Toru Anezaki
Archive | 2004
Taiji Ema; Hideyuki Kojima; Toru Anezaki; Shinichi Nakagawa
Archive | 2002
Toru Anezaki; Shinichiroh Ikemasu
Archive | 2007
Toru Anezaki; Tomohiko Tsutsumi; Tatsuji Araya; Hideyuki Kojima; Taiji Ema
Archive | 2011
Toru Anezaki
Archive | 2008
Toru Anezaki
Archive | 2004
Toru Anezaki
Archive | 2004
Toru Anezaki; Tatsuji Araya; Taiji Ema; Hideyuki Kojima; Tomohiko Tsutsumi; 秀之 兒嶋; 智彦 堤; 徹 姉崎; 泰示 江間; 達次 荒谷
