Taiji Ema

A 40-ns 64-Mb DRAM with 64-b parallel data bus architecture

The authors describe circuit techniques for wide input/output (I/O) data path and high-speed 64-Mb dynamic RAMs (DRAMs). A hierarchical data bus structure using double-level metallization has been developed to form 64-b parallel data bus lines without increasing the chip size. A current-sensing data bus amplifier, developed to sense the 64-b data bus signal in parallel, has made the wide I/O data path structure possible. A direct-sensing type column gate circuit with the READ/WRITE separated select line scheme achieves 40-ns RAS access. A shielded bit-line three-dimensional stacked-capacitor cell with a double-fin storage capacitor stores sufficient charge while the bit-line capacitance shows a reasonable value for sensing the data. >

Advanced channel engineering achieving aggressive reduction of V T variation for ultra-low-power applications

We have achieved aggressive reduction of V<inf>T</inf> variation and V<inf>DD-min</inf> by a sophisticated planar bulk MOSFET named ‘Deeply Depleted Channel ™ (DDC)’. The DDC transistor has been successfully integrated into an existing 65nm CMOS platform by combining layered channel formation and low temperature processing. The 2x reduction of V<inf>T</inf> variation in 65nm-node has been demonstrated by matching SRAM pair transistors, 2x improvement in SRAM static noise margin (SNM) and 300 mV V<inf>DD-min</inf> reduction of 576Kb SRAM macros to 0.425 V using conventional 6T cell layout.

3-dimensional stacked capacitor cell for 16 M and 64 M DRAMS

A second-generation three-dimensional stacked capacitor cell has been developed. This cell has two significant features. One is that the three-dimensional feature of the storage capacitor has been considerably enhanced by means of a fine structure. The other is that bit lines have been formed before storage capacitor formation. Either of these features will lead to the realization of 16 M DRAMs (dynamic random-access memories), and both will be necessary to realize 64 M DRAMs.<<ETX>>

A 150-mhz 4-bank 64m-bit Sdram With Address Incrementing Pipeline Scheme

We developed a 150-MHz 64M-bit SDRAM with an address incrementing pipeline scheme. For a synchronous read/write operation, we divided the column access path into three pipeline stages [l]. To increase the operating speed, we developed an address incrementing pipeline scheme, which can concurrently access data at two consecutive addresses. Using this scheme, the area penalty is 1.5% more than that of the conventional DRAM. For high frequency signals, we used T

Fabrication of 64 M DRAM with i-line phase-shift lithography

New phase-shift lithography applicable to all device patterns has been developed which combines pattern formation with the shifter alone and edge contrast enhancement with the shifter. Using it one can make 0.3 mu m patterns with i-line photolithography. A 64 M DRAM having memory cells unrestricted by angular considerations was designed for use with this lithography, and experimental 64 M DRAM chips were fabricated. The technique eliminates the need for special pattern design such as assistant patterns. Since it requires only the original design pattern, it is easy to apply to fabrication.<<ETX>>

A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits

65nm Deeply Depleted Channel (DDCTM) transistors have been fabricated with a halo-free, un-doped epitaxial channel and enable reduced threshold voltage (VT) variation, lower supply voltage (VCC), enhanced body effect and IEFF. Digital circuits made using this technology show benefits ranging from 47% power reduction to 38% frequency increase. Analog circuits exhibit 4x greater amplifier gain despite lower VDD, and current mirror mismatch (both global and local) shows 40% and 30% reduction for NMOS and PMOS, respectively.

Dielectrically encapsulated trench capacitor cell

A DRAM cell with an improved trench structure, capacitor has been developed for 16M DRAMs. The capacitor is formed within a trench with polysilicon to polysilicon structure. Covering the storage electrode with the cell-plate makes this cell free from punch-through between adjacent cells. The whole capacitor is coverd with a dielectric layer and there is no interference between cells. An experimental cell was fabricated, using 4M DRAM technology. Measured data indicates that this cell is suitable for the forthcoming 16M DRAMs.

Embedded Flash on 90nm Logic Technology & Beyond for FPGAs

We have successfully integrated an embedded flash technology into a 90 nm leading edge logic technology to realize superior FPGA products with only 10% additional process steps. The stacked gate memory cell is completely compatible with Cu and a low-k interconnection and has excellent flash reliability. Achieving the same logic performance as the non-embedded technology maximizes the utilization of design resources between the non-embedded technology and the embedded flash technology.

A 15 ns 16 Mb CMOS SRAM with reduced voltage amplitude data bus

A 15-ns 16-Mbit CMOS SRAM which uses a reduced voltage amplitude data bus and a hierarchical sense amplifier scheme is described. The SRAM is organized as 4 Mwords*4 bits. Fast access time and low power dissipation are obtained by a reduced-voltage-amplitude data bus connected to a latched cascaded sense amplifier and current sense amplifier. The waveforms of the address input and the data output lines at room temperature with a 3-V supply are shown. The access time is typically 15 ns, with an active current consumption of 55 mA at 3.0 V and 30 MHz.<<ETX>>

A 70ns 4Mb DRAM in a 300mil DIP using 4-layer poly

divided into four 1Mb blocks which have its own clock drivers. Because only one of them operates in each read or write cycle, the RAM dissipates less than 40mA (typical). Each lhlb block has two arrays of column decoders with sense amplifiers on both sides of them. Figure 2 shows sense amplifier circuit. Isolation transistors are inserted between bitlines and an N-channel sense amplifier to isolate noises from the bit lines and to amplify a minute signal correctly. P-channel cross-coupled transistors are arranged outside the isolation transistors to restore a bit line and a cell to full VCC level.