Hirohiko Mochizuki

A 256 Mb SDRAM using a register-controlled digital DLL

This 256 Mb synchronous DRAM with 1 ns clock access is stable against temperature, voltage, and process variation by use of an innovative register-controlled delay locked loop (RDLL). Unlike most conventional high-density DRAMs, the bit-lines are placed above the storage capacitors in this DRAM to relax design rules of the core area. The noise issues are analyzed and resolved to help implement the technology in mass production of 0.28 to 0.24 /spl mu/m 200 MHz DRAMs.

A 150-mhz 4-bank 64m-bit Sdram With Address Incrementing Pipeline Scheme

We developed a 150-MHz 64M-bit SDRAM with an address incrementing pipeline scheme. For a synchronous read/write operation, we divided the column access path into three pipeline stages [l]. To increase the operating speed, we developed an address incrementing pipeline scheme, which can concurrently access data at two consecutive addresses. Using this scheme, the area penalty is 1.5% more than that of the conventional DRAM. For high frequency signals, we used T

A 64K DRAM with 35 ns static column operation

A 64K dynamic RAM with a function mode similar to static memory operation is described. The device has multiplexed address inputs and a one-address strobe clock (RAS). After a row address is applied to the device, column selection is performed as in static memory, resulting in fast cycle time and simplicity of use. Column address access time and cycle times of 35 ns are achieved. The device has some other functions to reduce critical timings. Address transition detector circuits are used for column selection. An improved column decoder is provided to allow column address input skew. The device uses NMOS single transistor memory cells and is packaged in a standard 300-mil 16-pin DIP.

A 70ns 4Mb DRAM in a 300mil DIP using 4-layer poly

divided into four 1Mb blocks which have its own clock drivers. Because only one of them operates in each read or write cycle, the RAM dissipates less than 40mA (typical). Each lhlb block has two arrays of column decoders with sense amplifiers on both sides of them. Figure 2 shows sense amplifier circuit. Isolation transistors are inserted between bitlines and an N-channel sense amplifier to isolate noises from the bit lines and to amplify a minute signal correctly. P-channel cross-coupled transistors are arranged outside the isolation transistors to restore a bit line and a cell to full VCC level.

A 35ns 64K static column DRAM

A 64K by l b DRAM with multiplexed address inputs, packaged in a standard 300-mil wide 16 pin DIP, but with only one address strobe clock (RAS), will be reported. After one row address is selected with the RAS clock, as in normal multiplexed devices, column address selection (one of the 2561, boundarylrow) can be performed in a manner similar to static memory: data from the output changes in accordance with the change of column address without an address strobe clock. Access time from the columnzdress, and cycle time are typically 3511s. The deaffords CS (Chip select) instead of column address strobe (CAS), enabling or disabling the output at high speed. Typical chip select access time is less than 12ns. In write operation the falling edge of write enable (WE) latches the column address and Data In, and the write operation period extends automatically to the time when the device indicates the completion of writing; write time out. Following read or write operation starts immediately according to the state of WE. Figure 1 illustrates the concept of static column operation. The storage cells, sense amplifiers, and row decoders are almost the same as those of current 64K DRAMS. The sense amplifiers are fully dynamic with active pull up circuits. Word lines are pushed above Vcc to utilize the full charge of cells.