Masaki Furumai

Fast switching 4H-SiC V-groove trench MOSFETs with buried P + structure

4H-SiC trench MOSFETs with novel V-groove structures have been investigated. We have fabricated trench MOSFETs with the inclined 4H-SiC{0-33-8} face [1, 2] as trench sidewalls for the channel region, resulting in a low specific on-resistance owing to the superior MOS interface properties. In addition, by using buried p+ regions inside the drift layer, a high voltage avalanche breakdown without oxide break was realized as well. The specific on-resistance and breakdown voltage were 3.5 mΩ cm2 (VGS = 18 V, VDS = 1 V) and 1700 V, respectively. The switching capability of the trench MOSFET demonstrated fast dynamic characteristics without adverse effects in comparison to the trench MOSFET without buried p+ regions. Typical turn-on and turn-off time for the switching were estimated to be 92 ns and 27 ns, respectively from the resistive load switching measurements at a drain voltage of 600V.

600 V -Class V-Groove SiC MOSFETs

The authors applied a thick gate oxide layer at the trench bottoms to 600 V class truncated V-groove MOSFETs of which MOS channels were formed on 4H-SiC (0-33-8) facets and validated the static and switching characteristics. The specific on-resistance and the threshold voltage were 3.6 mΩ cm2 (VGS=18 V, VDS=1 V) and about 1 V (normally-off), respectively. The breakdown voltage of the MOSFET with a thick oxide layer was 1,125 V (IDS=1 μA). The switching losses during turn-on and turn-off operations were estimated to be 105.8 μJ and 82.5 μJ (300 V, 10 A) at room temperature. The switching characteristics exhibited low temperature dependence for turn-on/off time.

The optimised design and characterization of 1200 V / 2.0 mΩ cm 2 4H-SiC V-groove trench MOSFETs

V-groove trench MOSFETs with the 4H-SiC{0-33-8} face as the trench sidewall for the channel region have been investigated. The on-resistance and breakdown voltage strongly depend on the aperture ratio of the buried p+ regions. The VMOSFETs with the buried p+ regions of 71% on a 6-inch wafer exhibited a low specific on-resistance of 2.0 mΩ cm2 with 1200 V blocking voltage. The threshold voltage is 2.3 V at 175°C, which shows the VMOSFETs have tolerability for an erroneous ignition under high temperature. The switching capability showed low switching losses over DMOSFETs on 4° off 4H-SiC(0001) face and normal operation under fast switching repetitive test (40 Vns-1). The stability of the threshold voltage was demonstrated by HTGB tests.

Gate oxide reliability of 4H-SiC V-groove trench MOSFET under various stress conditions

The authors reported the optimization of the 4H-SiC V-groove Trench MOSFET (VMOSFET) structure in a previous conference (ISPSD2015). The VMOSFET has the buried p+ regions in the epitaxial layer to protect the trench bottom oxide. In this study, we characterized the long-term gate oxide reliability of the VMOSFETs under various stress conditions such as the gate bias or the drain bias. The VMOSFETs showed the Qbd of 28 Ccm-2 under the constant current stress TDDB measurement at RT. The threshold voltage of the VMOSFETs did not change significantly (|ΔVth|<; 0.12 V) under both the static and the switching gate bias conditions at 175°C for more than 1000 hours. The gate leakage current after the drain bias test did not change for over 6500 hours. In addition, the SCSOA of the VMOSFET was larger than 10 μsec.

The Influence of Surface Pit Shape on 4H-SiC MOSFETs Reliability under High Temperature Bias Tests

The influence of surface pit shape on 4H-SiC double implanted MOSFETs (DMOSFETs) reliability under a high temperature drain bias test has been investigated. Threading dislocations formed two types of pit shapes (deep pit and shallow pit) on an epitaxial layer surface. The cause of the failure was revealed to be an oxide breakdown above the pit generated at the threading mixed dislocation in both pit shapes. Weibull distributions between two types of pits were different. Although the DMOSFETs on the epitaxial layer with the deep pit show longer lifetime than those with the shallow pit, the epitaxial layer with the shallow pit is suitable to estimate the lifetime of the DMOSFETs because of a linearity of the Weibull plot. The lifetime of the DMOSFETs with the shallow pit was dominated by an oxide electric field. The maximum oxide electric field required to obtain the lifetime of more than 10 years was estimated to be 2.7 MV/cm.

Demonstration of 13-kV class junction barrier Schottky diodes in 4H-SiC with three-zone junction termination extension

The static and dynamic characteristics of 13-kV class 4H-SiC junction barrier Schottky (JBS) diodes with a three-zone junction termination extension (JTE) are presented. Using an anisotropy breakdown model, technology computer-aided design simulation of devices with a three-zone JTE agrees well with the obtained experimental results, correctly predicting a sharp drop in blocking voltage at high JTE acceptor concentrations. The forward voltage of the JBS diode at 75°C and a forward current of 500 mA is reduced to approximately one-ninth by that of 13 series-connected 1000-V Si PiN diodes. This suggests that conduction losses of traditional high-voltage circuits which conventionally use series-connected devices can be drastically reduced by replacing the series-connected devices with a single 13-kV class SiC JBS diode. Moreover, the reverse recovery current waveform of the 13-kV class SiC JBS diode shows that these diodes have lower reverse recovery losses than a 13-kV SiC PiN diode.

99.9% BPD Free 4H-SiC Epitaxial Layer with Precisely Controlled Doping upon 3 x 150 mm Hot-Wall CVD

Epitaxial growth of 4H-SiC on 150 mm wafers has been investigated using experimental results and numerical simulations toward the goal of BPDs reduction and doping uniformity control in the epitaxial layer. We have reported analyses of the temperature distribution dependence of the doping uniformity and BPDs propagations on the 3 x 150 mm multi-wafer CVD epitaxial growth. By optimizing epitaxial growth conditions, we have demonstrated an excellent doping and thickness uniformity and a 99.9% BPD free region, simultaneously.

Low on-resistance and fast switching of 13-kV SiC MOSFETs with optimized junction field-effect transistor region

In this paper, a 13-kV SiC MOSFET with a retrograde doping profile in junction field-effect transistor (JFET) regions, which were implanted by nitrogen ions with multiple energies, has been developed for power supplies of X-ray generators and electron guns with an accelerating voltage greater than 10 kV. A JFET region was optimized with device simulation to reduce on-resistance. A SiC MOSFET with an optimized JFET region was fabricated with a 5 mm × 5 mm die size. The specific on-resistance (R<inf>onA</inf>) was estimated to be 169 mΩ·cm². The blocking voltage (BV<inf>DSS</inf>) of 13.1 kV was obtained at 10 μA/cm². Owing to a low electric field in the gate oxide (E<inf>ox</inf>), a threshold voltage (V<inf>th</inf>) shift within ± 0.06 V was achieved at the gate voltage of −15 V (equal to an electric field of −3 MV/cm) and 200 °C for 1000 hours. The dynamic test with inductive load resulted in turn-off and turn-on switching speeds of 75 kV/μs and 114 kV/μs, respectively, for the DC bus voltage of 10 kV at room temperature.