Kosuke Uchida

Blocking Characteristics of 2.2 kV and 3.3 kV-Class 4H-SiC MOSFETs with Improved Doping Control for Edge Termination

Blocking characteristics of 2.2 kV and 3.3 kV -class 4H-SiC MOSFETs with various doping conditions for the edge termination region have been investigated. By optimizing the implanted dose into the edge termination structure consisting of junction termination extension (JTE) and field limiting ring (FLR), a breakdown voltage of 3,850 V for 3.3 kV -class MOSFET has been attained. This result corresponds to about 95% of the approximate parallel-plane breakdown voltage estimated from the doping concentration and the thickness of the epitaxial layer. Implanted doping for the JFET region is effective in reducing JFET resistance, resulting in the specific on-resistance of 14.2 mΩcm2 for 3.3 kV SiC MOSFETs. Switching characteristics at the high drain voltage of 2.0 kV are also discussed.

The optimised design and characterization of 1200 V / 2.0 mΩ cm 2 4H-SiC V-groove trench MOSFETs

V-groove trench MOSFETs with the 4H-SiC{0-33-8} face as the trench sidewall for the channel region have been investigated. The on-resistance and breakdown voltage strongly depend on the aperture ratio of the buried p+ regions. The VMOSFETs with the buried p+ regions of 71% on a 6-inch wafer exhibited a low specific on-resistance of 2.0 mΩ cm2 with 1200 V blocking voltage. The threshold voltage is 2.3 V at 175°C, which shows the VMOSFETs have tolerability for an erroneous ignition under high temperature. The switching capability showed low switching losses over DMOSFETs on 4° off 4H-SiC(0001) face and normal operation under fast switching repetitive test (40 Vns-1). The stability of the threshold voltage was demonstrated by HTGB tests.

Gate oxide reliability of 4H-SiC V-groove trench MOSFET under various stress conditions

The authors reported the optimization of the 4H-SiC V-groove Trench MOSFET (VMOSFET) structure in a previous conference (ISPSD2015). The VMOSFET has the buried p+ regions in the epitaxial layer to protect the trench bottom oxide. In this study, we characterized the long-term gate oxide reliability of the VMOSFETs under various stress conditions such as the gate bias or the drain bias. The VMOSFETs showed the Qbd of 28 Ccm-2 under the constant current stress TDDB measurement at RT. The threshold voltage of the VMOSFETs did not change significantly (|ΔVth|<; 0.12 V) under both the static and the switching gate bias conditions at 175°C for more than 1000 hours. The gate leakage current after the drain bias test did not change for over 6500 hours. In addition, the SCSOA of the VMOSFET was larger than 10 μsec.

The Influence of Surface Pit Shape on 4H-SiC MOSFETs Reliability under High Temperature Bias Tests

The influence of surface pit shape on 4H-SiC double implanted MOSFETs (DMOSFETs) reliability under a high temperature drain bias test has been investigated. Threading dislocations formed two types of pit shapes (deep pit and shallow pit) on an epitaxial layer surface. The cause of the failure was revealed to be an oxide breakdown above the pit generated at the threading mixed dislocation in both pit shapes. Weibull distributions between two types of pits were different. Although the DMOSFETs on the epitaxial layer with the deep pit show longer lifetime than those with the shallow pit, the epitaxial layer with the shallow pit is suitable to estimate the lifetime of the DMOSFETs because of a linearity of the Weibull plot. The lifetime of the DMOSFETs with the shallow pit was dominated by an oxide electric field. The maximum oxide electric field required to obtain the lifetime of more than 10 years was estimated to be 2.7 MV/cm.