Keiichi Higashitani

A bipolar-PMOS merged basic cell for 0.8 mu m BiCMOS sea-of-gates

To improve the density of BiCMOS sea-of-gates, bipolar and PMOS transistors are merged to form compact basic cells combined with the gate isolation technique. This structure occupies only 12% of the conventional bipolar transistor area. The density of the basic cell increases by 60% compared with conventional cells. The pull-up BiCMOS circuit achieves the fastest gate delay of 200 ps. A 16-bit multiplier in the test chip fabricated with 0.8 mu m BiCMOS technology operates at 18 ns delay time.<<ETX>>

Submicron CBiCMOS technology with new well and buried layer formed by multiple energy ion implantation

A simple 0.6- mu m complementary BiCMOS (CBiCMOS) technology was developed without an epitaxial layer. The wells and the buried layers for all transistors were formed by only three steps of masking layers, using multiple energy ion implantation with megaelectronvolt energy. The problem of the secondary defect induced by high dose and high energy ion implementation was solved by using the rapid thermal annealing technique. The cutoff frequencies for n-p-n and p-n-p were 11 GHz and 5 GHz, respectively. Using this technology, high-performance LSIs including mixed analog/digital devices can be developed.<<ETX>>

A bipolar-PMOS merged basic cell for 0.8 mu m BiCMOS sea of gates

A compact basic cell for BiCMOS sea-of-gates (SOG) circuits was developed using a bipolar-PMOS merged structure and gate-isolated bipolar transistors. The new cell structure reduces the cell area using the bipolar-PMOS merged transistors. The cell has no restrictions regarding macrocell placement because it has no shared element. The cell density is 60% higher than that of conventional cells. Three types of circuits are provided for a macrocell using the basic cell. The pull-up BiCMOS circuit, one of the circuit alternatives, obtains the shortest gate delay with average load capacitance and high density comparable to a pure CMOS density. The gate delay of 200 ps was achieved with the pull-up BiCMOS two-input NAND gate fabricated with 0.8- mu m BiCMOS technology. >