Toshiaki Inoue

250-MHz BiCMOS super-high-speed video signal processor (S-VSP) ULSI

A 250-MHz, 16-b, fixed-point, super-high-speed video signal processor (S-VSP) ULSI has been developed for constructing a video teleconferencing system. Two major technologies have been developed. One is a high-speed large-capacity on-chip memory architecture that achieves both 250-MHz internal signal processing and 13.5-MHz input and output buffering. The other is a circuit technology that achieves 250-MHz operations with a convolver/multiplier, an arithmetic logic unit (ALU), an accumulator, and various kinds of static RAMs (SRAMs). A phase-locked loop (PLL) is also integrated to generate a 250-MHz internal clock. The S-VSP ULSI, which was fabricated with 0.8- mu m BiCMOS and triple-level-metallization technology, has a 15.5-mm*13.0-mm area and contains about 1.13 million transistors. It consumes 7 W at 250-MHz internal clock frequency with a single 5-V power supply. >

A 500 MHz, 32 bit, 0.4 /spl mu/m CMOS RISC processor

A 500 MHz, 32 bit RISC microprocessor has been experimentally developed using an 8-stage pipelined architecture and high-speed circuits, including a 500 MHz 1 kilobyte double-stage pipelined cache, a 1.8 ns register file, a double-stage binary look-ahead carry (BLC) adder circuit, and a 500 MHz phase locked loop (PLL) frequency multiplier. Newly developed circuit-integrating techniques include a stacked power-line structure, which serves as a noise shield and also provides low bounce, a low voltage-swing interface circuit with on-chip adjustable termination resistors, a small-skew clock distribution method, and a clock synchronization circuit which provides small-skew clock among LSI chips. About 200000 transistors are integrated into a 7.90 mm/spl times/8.84 mm die area with 0.4 /spl mu/m CMOS fabrication technology. Power dissipation is 6 W at a 500 MHz operation and 3.3 V supply voltage. >

A 300-MHz 16-b BiCMOS video signal processor

A 300-MHz 16-b full-programmable parallel-pipelined video signal processor ULSI has been developed. With multifunctional arithmetic units to achieve parallel vector processing, and with a phase-locked-loop (PLL) type clock generator to help attain the 300-MHz internal operating speed, this ULSI is able to attain, with only one chip, 30-frame-per-second full-CIF video data coding based on CCITT H.261. Two different types of pass-transistor BinMOS circuits have been developed to help achieve an access time of 3 ns for a 146-kb SRAM and for data buses. Fabricated with a 0.5- mu m BiCMOS and triple-layer metallization process technology, the video signal processor ULSI contains 1.27-million transistors in a 16.5*17.0-mm/sup 2/ die area. >

A programmable clock generator with 50 to 350 MHz lock range for video signal processors

Using 0.5-/spl mu/m CMOS triple-layer Al technology, a programmable clock generator based on a PLL (phase-locked loop) circuit has been developed for use as an on-chip clock generator in a 300-MHz video signal processor. It generates an internal clock whose frequency is an integral multiple of an external clock frequency, and its oscillating frequency ranges from 50 to 350 MHz. Experimental results show that the clock generator generates a 297-MHz clock with jitter reduced to 180 ps with a 27-MHz input clock, and that it oscillates at up to 348 MHz with a 31.7-MHz input clock.

A 2.4-ns, 16-bit, 0.5-/spl mu/m CMOS arithmetic logic unit for microprogrammable video signal processor LSIs

A 16-b arithmetic logic unit (ALU) has been developed for achieving high-speed microprogrammable video signal processor LSIs. The ALU employs a parallel architecture with newly developed high-speed circuit operations, including highly parallel addition, operand look-ahead overflow detection, and carry select zero-flag detection. The unit contains 6,272 transistors in a 1.50 mm /spl times/ 1.09 mm die area using 0.5-/spl mu/m CMOS process technology, and 2.4-ns ALU operations have been successfully achieved.

A 300-MHz, 16-bit, 0.5-/spl mu/m BiCMOS digital signal processor core LSI

A 300-MHz, 16-bit, 0.5-/spl mu/m BiCMOS digital signal processor (DSP) core LSI, which employs a parallel processing architecture, 300-MHz redundant binary arithmetic units, and a sophisticated high-performance electrical design, has been developed for video signal processing. Measured clock skew and critical path delay are less than 80 ps and 2.6 ns, respectively. It has a parallel processing architecture capable of discrete cosine transform (DCT) operations for efficient motion picture coding in video signal processing.

Cache-processor coupling: a fast and wide on-chip data cache design

This paper presents a new data cache design, cache-processor coupling, which tightly binds an on-chip data cache with a microprocessor. Parallel architectures and high-speed circuit techniques are developed for speeding address handling process associated with accessing the data cache. The address handling time has been reduced by 51% by these architectures and circuit techniques. On the other hand, newly proposed instructions increase data cache bandwidth by eight times. Excessive power consumption due to the wide-bandwidth data transfer is carefully avoided by newly developed circuit techniques, which reduce dissipation power per bit to 1/26. Simulation study of the proposed architecture and circuit techniques yields a 1.8 ns delay each for address handling, cache access, and register access for a 16 kilobyte direct mapped cache with a 0.4 /spl mu/m CMOS design rule. >

A 1.5% jitter PLL clock generation system for a 500-MHz RISC processor

We have developed a clock generation system for RISC processors. The system consists of two parts of a PLL, a frequency multiplier, and a phase aligner. The multiplier can multiply the input clock frequency by 2, 4, and 8, and can accomplish a wide frequency range of output clocks, from 60 MHz to 660 MHz. Jitter is reduced to 1.5% of the output clock period by separating the clock generation system into a frequency multiplier and a phase aligner, and by developing a new differential loop filter with high sensitivity phase detection. The phase aligner reduces clock skew between the processor and peripheral LSIs. The system is fabricated with 0.4-/spl mu/m CMOS triple-layer Al process technology and operated at 3.3 V.<<ETX>>

A 500 MHz 32b 0.4 /spl mu/m CMOS RISC processor LSI

This 500 MHz, 32b, reduced-instruction-set-computer (RISC) microprocessor uses 0.4 /spl mu/m CMOS technology. The microprocessor has an 8-stage pipelined data path. The 8 pipeline stages are: (1) instruction fetch 1 (I1); (2) instruction fetch 2 (I2); (3) register file fetch and instruction decode (RF); (4) execution 1 (E1); (5) execution 2 (E2); (6) data memory access 1 (D1); (7) data memory access 2 (D2); and (8) register file write-back (WB). The microprocessor includes a 32w/spl times/32b two-read/one-write register file, two double-stage pipelined 1 kB caches for both instructions and data, a 32b double-stage pipelined adder and barrel shifter, and a phase-locked loop circuit (PLL). The PLL multiplies input clock frequency by 2, 4 or 8 to obtain a 500 MHz internal clock.<<ETX>>