Tadahiko Horiuchi

Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design

This paper, focusing on the effect of a plasma-enhanced CVD (PECVD) nitride contact-etch-stop layer, reports that process-induced mechanical stress affects the performance of short-channel CMOSFETs. We argue that the internal stress in the nitride layer changes transconductance (G/sub m/), thereby degrading NMOSFET performance by up to 8% and improving PMOSFET performance up to 7%. These performance changes are caused by changes of the electron and hole mobilities, so a precise transistor model considering this mobility change is necessary for deep-submicron transistor design.

The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling

This paper presents a new reliability scaling scenario for CMOS devices with direct-tunneling ultra-thin gate oxide. Device degradation due to bias-temperature instability (BTI) was studied. First, the stress voltage dependence of BTI results indicate that the direct-tunneling electron and/or hole transport does not play a major role in the degradation mechanism. Secondly, it was found that the threshold voltage change caused by BTI for the PMOSFET limits the device lifetime, which is shorter than that defined by hot-carrier induced degradation for the NMOSFET. It originates from the difference of supply voltage dependence between BTI and hot-carrier degradation.

NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10-/spl mu/m gate CMOS generation

We investigated the degradation of device reliability due to Negative Bias Temperature Instability (NBTI) of PMOSFET with ultrathin gate oxide. It was experimentally demonstrated that the chemical reactions at the gate oxide/substrate interface and/or diffusion of hydrogen related species are the major cause of the NBTI. We also found that nitridation of gate oxide enhances NBTI. In order to suppress the NBTI, the density of hydrogen terminated silicon bond at the interface needs to be minimized. Thus, the concentration of nitrogen in thin gate oxide has to be optimized in terms of the reliability reduction due to NBTI.

A 16 Mb 400 MHz loadless CMOS four-transistor SRAM macro

0.18 /spl mu/m logic process technologies have recently been used to develop a loadless CMOS four-transistor SRAM cell (4T-cell) whose size (1.934 /spl mu/m/sup 2/) is only 56% that of a conventional six-transistor SRAM cell (6T-cell). Using this 4T-cell technology. The authors present a 16 Mb, 400 MHz SRAM macro which features: (1) an end-point dual-pulse driver (EDD) for stable data hold and minimum cycle time, (2) word-line-voltage-level compensation (WLC) for stable static data hold, and (3) an all-adjoining twist bit-line (ATBL) to reduce bit-line coupling capacitance.

A simple method to evaluate device lifetime due to hot-carrier effect under dynamic stress

A method to evaluate hot-carrier-induced NMOSFET degradation under dynamic stress is discussed, based on an empirical relation between device lifetime and substrate current in static stress. The device lifetime τ under dynamic stress is given by\tau = A.I_{sub,peak}^{-2.5}/R, whereI_{sub,peak}is the peak value of pulsive substrate current and R is its duty ratio. The device lifetime experimentally obtained in an inverter circuit is in good agreement with the calculation results obtained from the proposed method. This method is useful to estimate device lifetime in actual circuit operational conditions.

An asymmetric sidewall process for high performance LDD MOSFET's

An asymmetric LDD sidewall spacer technology is presented which gives a high drivability of LDD MOSFET without sacrificing hot carrier immunity. The asymmetric spacer is fabricated by using a selective oxide deposition technique. The process implemented in a CMOS fabrication sequence requires no additional masking step. The fact that no reliability problems are introduced in the transistor characteristics by the selective oxide deposition process is also examined. >

Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI

This paper presents a new circuit scheme called a transient sensitive accelerator (TSA) circuit for highly resistive interconnects. The TSA can reduce both delay time and crosstalk voltage. Using the TSA with an interconnect length of 30 mm reduces delay time and crosstalk voltage by 29% and 20%, respectively. A further advantage is that the TSA operates in self-time and thus can be applied to bidirectional signal communication.

Effect of mechanical stress induced by etch-stop nitride: impact on deep-submicron transistor performance

Abstract This paper reports that process-induced mechanical stress affects the performance of short-channel MOSFETs, and focuses on the effect of a plasma-enhanced CVD nitride contact-etch-stop layer. The stress in the channel region induced by the nitride layer changes transconductance ( G m ), thereby changing the device performance. When the nitride stress varies from +300 MPa (tensile) to −1.4 GPa (compressive), NMOSFET performance degrades by up to 8% and PMOSFET performance improves up to 7%. These changes are caused by the modulation of the electron/hole mobilities, so controlling process-induced stress and considering this mobility change in a precise transistor model are necessary for deep-submicron transistor design.

Application of Fluorinated Amorphous Carbon Thin Films for Low Dielectric Constant Interlayer Dielectrics

Fluorinated amorphous carbon thin films (a-C:F) for use as low-dielectric-constant interlayer dielectrics are deposited by helicon-wave plasma-enhanced chemical vapor deposition using fluorocarbon compounds as a source material. The a-C:F films can be grown from C4F8 at a high deposition rate (above 400 nm/min) and they are thermally stable up to 350°C. The addition of bias power to the substrate makes it possible to completely fill gaps in the wiring (space 0.35 µm, height 0.65 µm) with the a-C:F film. To protect the a-C:F film during further processing, a SiO2 film is deposited to add mechanical strength and resistance to the oxygen plasma used to remove resist materials. The adhesion between the a-C:F and SiO2 films is dramatically improved by inserting an adhesion promoter consisting of a-C:H and Si-rich SiO2. By using the a-C:F and SiO2 dielectrics and chemical mechanical polishing (CMP) process, globally planarized 3-level metallization is achieved. The a-C:F dielectric can reduce inter-line capacitance close to a half value as compared with the conventional SiO2 dielectrics.

A 0.25-/spl mu/m CMOS 0.9-V 100-MHz DSP core

This paper describes a 0.25-/spl mu/m CMOS 0.9-V 100-MHz DSP core which is composed of a 2-mW 16-b multiplier-accumulator and a 1.5-mW 8-kb SRAM. High-speed operation with a supply of less than 1 V has been achieved by developing 0.25-/spl mu/m CMOS technology, reducing threshold voltage to 0.3 V, developing tristate inverter 3-2/4-2 adders for the multiplier, realizing small bit-line swing operation for the SRAM, and so on. The adder circuits operate faster than conventional adders at low supply voltages. In addition, short-circuit current and area for diffusion contact are reduced. Small bit-line swing operation has been realized by using a device-deviation immune sense amplifier. Leakage current during sleep mode was reduced by the use of high threshold voltage MOSFETs.