Toshiaki Ozeki

An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects

An 11-b 300-MS/s double sampling pipelined ADC with on-chip digital calibration for memory effects is presented. In double-sampling pipelined ADC architecture, memory effect of residual charge occurs due to sharing an op-amp between two channels of pipelined ADC. The proposed foreground calibration technique removes the memory effect error in digital domain without additional analog circuit. Thus, the technique simplifies the analog circuits, which extends the operation speed over 300 MHz. The chip is fabricated in a 40 nm CMOS and occupies 0.42 mm2 including digital calibration logic. The ADC consumes 40 mW from a 1.8 V supply, and FoM is 0.24-pJ/conversion-step.

A 2GS/s 8b time-interleaved SAR ADC for millimeter-wave pulsed radar baseband SoC

This paper presents a 2 GS/s 8-bit 16× time-interleaved (TI) ADC for millimeter-wave pulsed radar baseband SoC in 40nm CMOS. An extremely-compact foreground timing calibration suppresses sampling clock skews among sub-ADCs within 400fs. Measured SFDR and SNDR at 1GHz full-Nyquist is therefore enhanced by 16dB and 11dB, respectively. Unlike conventional calibration based on redundant ADCs or DSP-assisted calculations, just a few small resistors and a capacitor are needed, resulting in only 0.4% area penalty. This area saving enables the compact integration of the radar SoC with beamforming where 8-channel TI-ADCs occupy the dominant chip area otherwise. Even though this is foreground, no system performance is sacrificed because the calibration sequence is closed-loop and fast enough to be executed during an existing calibration interval in a periodic beam transmission sequence. Thanks to the foreground scheme, the TI-ADC including the input buffer consumes only 54.2mW and 355fJ/step.

A 2-GS/s 8-bit Time-Interleaved SAR ADC for Millimeter-Wave Pulsed Radar Baseband SoC

This paper presents a 2-GS/s 8-bit 16

An 11b 300MS/s 0.24pJ/conversion-step Double-Sampling Pipelined ADC with on-chip full digital calibration for all nonidealities including memory effects

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CLOCK SIGNAL GENERATING DEVICE AND ANALOG-DIGITAL CONVERSION DEVICE

time-interleaved (TI) analog-to-digital converter (ADC) for a millimeter-wave pulsed radar baseband system-on-chip (SoC). To suppress sampling timing errors among sub-ADCs, a foreground timing-skew calibration technique with small additional circuits is proposed. Measured spurious-free dynamic range and signal-to-noise distortion ratio at 1-GHz full Nyquist is, therefore, enhanced by 16 and 11 dB, respectively. Unlike conventional calibration techniques based on redundant ADCs or complicated digital calculations, additional circuit components are only several small resistors and a capacitor, resulting in only 0.4% area penalty. This area saving enables the compact integration of the radar baseband SoC with digital beamforming, where eight-channel TI-ADCs occupy the dominant chip area otherwise. Even though this is foreground, no system performance is sacrificed because the calibration sequence is closed loop and fast enough to be executed during an existing calibration interval in a periodic beam transmission sequence. The TI-ADCs are embedded on industrial SoC in a 40-nm CMOS process. The power consumption including the input buffer and the reference buffer is 54.2 mW from a 1.1-V supply, and figure of merit is 355 fJ/conversion step.