Takuji Miki

A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise

SAR-ADC power efficiency has improved due to its digitally oriented nature that utilizes the high switching speed of nanometer CMOS processes. In recent reports, time-interleaving techniques and multi-bit-per-cycle conversion have boosted speed to the GHz sampling range at low power consumption. However, to achieve SNR of >70dB at moderate sampling speed, SARs still need a lot of power, namely tens of mW [1-2]. In [1], a very high SNR of 90dB is achieved by a stage to amplify residue charge, which is one of the reasons for the 105mW power consumption at 12.5MS/s. In [2], 8× oversampling and a static current pre-amplifier for the comparator improve SNR to 88dB, but the ADC still consumes 66mW. In [3], digital calibration achieves an SNDR of 71dB at 3mW, but double conversion limits the sampling speed to 22.5MS/s.This paper describes a SAR ADC with 71dB SNDR that runs at 50MS/s and consumes 4.2mW. The ADC uses 3 SNDR-enhancement techniques that utilize noise and that have good compatibility to low-voltage fine digital processes.

Design methods for pipeline & delta-sigma A-to-D converters with convex optimization

In system LSIs, costs of analog circuits are getting increased relatively for rapid cost reduction of digital circuits. To satisfy given specifications in the analog design, including low power and small area, designers have to select an optimal solution among large combination of the following alternatives: which architecture should be adopted; what type of transistors should be taken; and whether digitally assisting technologies should be used or not, etc. A design based on experience and intuition cannot lead to the optimum in a short time. A comprehensive approach to the optimization, based on circuit theory, is now required. Convex optimization procedure can solve the formulae which represent circuit performance with over hundreds of design variables. We have constructed optimization environments for pipelined and delta-sigma analog-to-digital converters (ADCs) in consideration of the digitally assisting techniques and layout constraints. Both 12-bit pipelined ADCs and a 5th-order delta-sigma modulator were designed with the optimizer, and achieved top-ranked power efficiency.

An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects

An 11-b 300-MS/s double sampling pipelined ADC with on-chip digital calibration for memory effects is presented. In double-sampling pipelined ADC architecture, memory effect of residual charge occurs due to sharing an op-amp between two channels of pipelined ADC. The proposed foreground calibration technique removes the memory effect error in digital domain without additional analog circuit. Thus, the technique simplifies the analog circuits, which extends the operation speed over 300 MHz. The chip is fabricated in a 40 nm CMOS and occupies 0.42 mm2 including digital calibration logic. The ADC consumes 40 mW from a 1.8 V supply, and FoM is 0.24-pJ/conversion-step.

A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques

This paper presents a SAR ADC with 71 dB SNDR and 85 dB SFDR at 50 MS/s while keeping low power consumption of 4.2 mW. To achieve high resolution without large increase of power, several SNR and SFDR enhancement techniques are proposed. Firstly, the ADC repeats comparison of LSB by using redundant DAC to average comparator noise and improve SNR. The technique also corrects settling error adaptively, which extends operation speed to 50 MHz even though extra comparison period is added for averaging. Secondly, simple filtering method for reducing DAC noise is introduced to achieve further improvement of SNR. Finally, new dithering method is proposed to enhance SFDR. Injecting noise-shaped, multi-valued and uniform-distributed dither to input of the ADC, spurs caused by capacitance mismatches of DAC can be suppressed more effectively compared with conventional dithering. These techniques can be realized by simple circuits in addition to a basic SAR ADC configuration and do not need high power consumption. The chip is fabricated in a 90 nm CMOS process and occupies 0.1 mm 2 including all correction logic. The ADC achieved a peak figure of merit (FoM) of 168.7 dB.

12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan

A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor is reported. Multiple touch points are detected by a two-step dual-mode capacitance scan, where self- and mutual-capacitance measurements are hierarchically performed in two steps to reduce scan time that is otherwise increased due to high resolution. 160 dedicated row and column ADCs are used for the parallel read-out to further reduce scan time. A time-domain digital conversion that uses a counter-based slope ADC significantly reduces power and area for the parallel ADC approach. The signal attenuation due to the sensor capacitance reduction in the 1mm fine-pitch electrode is compensated by using thorough noise-reduction techniques in the sensor analog front-end (AFE). A 0.35μm CMOS prototype demonstrates 41dB SNR with >3× higher pitch resolution, >10× faster touch-point scan, 12× and 4× higher energy and area efficiency compared to state-of-the-art touch sensors [1,2].

A 1 mm Pitch

A 1 mm pitch 80 X 80 channel 322 Hz framerate capacitive multitouch distribution sensor has been developed. High-resolution multiple touch points are detected including touch-strength distribution around them. A two-step dual-mode capacitance scan scheme is proposed, where self- and mutual-capacitance measurements are hierarchically performed in two steps to increase the frame scan rate that is otherwise reduced due to high resolution. 160 row-and-column dedicated parallel ADCs further increase the scan rate. A time-domain counter-based slope ADC suppresses power and area penalty for the parallel ADC approach. A signal attenuation due to the sensor capacitance reduction in the high resolution is compensated by thorough noise-reduction techniques in the sensor analog frontend (AFE). A prototype in 0.35 μm CMOS demonstrates 41 dB signal-to-noise ratio (SNR) with >5× tighter sensor-channel pitch, >10× faster touch-point scan, >10× and >4× higher energy and area efficiency to the state-of-the-art touch distribution sensors.

80 \times 80

A 97.99 dB SNDR, 2 kHz bandwidth noise-shaping SAR ADC was fabricated in 28 nm CMOS process. By integrating residue of 12 bit SAR AD conversion with 3rd order integrator, Σ modulation is achieved and noise floor of AD conversion is shaped. Distortion due to mismatch of capacitive DAC is eliminated by introducing dynamic element matching (DEM) technique and by utilizing modulation dither effect. The ADC consumes 37.1 μW with 100 kHz sampling speed and achieves Schreiers figure of merit (FoMs) of 175.3 dB.

Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan

This paper presents a 2 GS/s 8-bit 16× time-interleaved (TI) ADC for millimeter-wave pulsed radar baseband SoC in 40nm CMOS. An extremely-compact foreground timing calibration suppresses sampling clock skews among sub-ADCs within 400fs. Measured SFDR and SNDR at 1GHz full-Nyquist is therefore enhanced by 16dB and 11dB, respectively. Unlike conventional calibration based on redundant ADCs or DSP-assisted calculations, just a few small resistors and a capacitor are needed, resulting in only 0.4% area penalty. This area saving enables the compact integration of the radar SoC with beamforming where 8-channel TI-ADCs occupy the dominant chip area otherwise. Even though this is foreground, no system performance is sacrificed because the calibration sequence is closed-loop and fast enough to be executed during an existing calibration interval in a periodic beam transmission sequence. Thanks to the foreground scheme, the TI-ADC including the input buffer consumes only 54.2mW and 355fJ/step.

A 97.99 dB SNDR, 2 kHz BW, 37.1 µW noise-shaping SAR ADC with dynamic element matching and modulation dither effect

This paper presents a 2-GS/s 8-bit 16

A 2GS/s 8b time-interleaved SAR ADC for millimeter-wave pulsed radar baseband SoC

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