Toshiaki Sano

A poly-silicon TFT with a sub-5-nm thick channel for low-power gain cell memory in mobile applications

This work presents a gain-cell solution in which a novel ultrathin polysilicon film transistor provides the basis for dense and low-power embedded random-access memory (RAM). This is made possible by the new transistors 2-nm-thick channel, which realizes a quantum-confinement effect that produces a low leakage current value of only 10/sup -19/ A at room temperature. The memory has the potential to solve the power and stability problems that static RAM (SRAM) is going to face in the very near future.

Single-electron-memory integrated circuit for giga-to-tera bit storage

A single-electron-based integrated circuit is presented. An 8/spl times/8 b memory-cell array demonstrates read/write, ushering in a new phase of research on single-electron devices.

Verify: key to the stable single-electron-memory operation

The impact of verify, which has been used in flash memory but has not been associated with single-electron memory, is analyzed and experimentally demonstrated. Using verify overcomes many obstacles to large-scale integration, including background charge variation, the inherent stochastic behavior of single-electron dynamics, and nanoscale structure variation, especially in naturally formed nanostructures, such as nano-silicon. A write/erase endurance of 10/sup 7/ cycles was demonstrated with nano-Si memory devices.

A 3-D single-electron-memory cell structure with 2F/sup 2/ per bit

Summary form only given. A 3-dimensional (3-D) single-electron memory cell, which achieves an area of 2F/sup 2/ per bit (where F is the feature size of the fabricated structures), is proposed. In the proposed vertically united cell (VUC), two cells are stacked vertically which only adds a few steps to the whole fabrication process. The results obtained demonstrate that the single-electron memory has a cost advantage over conventional memories in terms of giga-scale memories. Moreover, with the aim of producing single-electron memory LSI, MOS devices are fabricated on the same wafer as the VUCs, and this set-up shows successful operation.

Status of single-electron memories

This paper reviews the status of single-electron memories. First, one-transistor single-electron memory, which has been the basis of the recent rapid development in this field is reviewed. Next, technologies used in recent 128-Mb large scale integration demonstration are discussed. Finally, future challenges and remaining issues are discussed.

Impact of Coulomb blockade on low-charge limit of memory device

Using a new single-electron memory device having much better control of poly-Si and gate oxide than the reported one, stored-charge probability distribution is directly measured for the first time. This is made possible by the real-time electron counting capability of the memory device. The standard deviation of charge is found to be 0.6 electrons, which clearly demonstrates single-electron-level control capability of our device. The results agree excellently with our new dynamic Coulomb blockade model. Based on these results, the minimum number of stored electrons satisfying 1000-fit 1Gb reliability is revealed to be five.

Threshold cancelling logic (TCL): a post-CMOS logic family scalable down to 0.02 /spl mu/m

Simple refrigeration of room-temperature-optimized CMOS devices does not enable low-voltage operation, because threshold voltage is higher at low temperatures. It might be possible to optimize threshold voltage for low-temperatures, but low-temperature-optimized CMOS suffers from a high leakage current at room temperature. This makes testing of the LSIs difficult. Burn-in testing with high temperature acceleration of feature modes would be particularly difficult because of the thermal runaway characteristics of the subthreshold current. This post-CMOS circuit family, threshold cancelling logic (TCL), can be scaled down to 0.02 /spl mu/m, corresponding to three generations smaller than conventional CMOS circuits.

SESO memory: A 3T gain cell solution using ultra thin silicon film for dense and low power embedded memories

This work presents a gain-cell solution in which a novel ultrathin poly-silicon film transistor provides the basis for dense and low-power embedded random-access memory. This is made possible by the 2-nm-thick channel of the new transistor (single-electron shut off transistor, or SESO transistor), which realizes a quantum-confinement effect that produces a low leakage current value of only 10/sup -19/ A at room temperature. Combining with vertical SESO structure, 3T gain cell achieves 1/3 the cell area of SRAM. Using circuit techniques, power consumption of SESO memory is expected to be lower than SRAM. The memory has potential to solve the power and stability problem that SRAM is going to face in the near future.

A cavity channel SESO embedded memory with low standby-power techniques

A 22F/sup 2/ 3-transistor dynamic memory cell, based on a newly fabricated cavity channel SESO (single-electron shutoff) transistor is proposed for low-power mobile SOCs. The ultra-low leakage SESO device is formed above the bulk devices to yield the small cell size. With low-power techniques, this memory can achieve nearly an order of magnitude lower standby power than conventional memory. A 1 Mbyte SESO embedded memory core is estimated to have a standby power consumption of 24.2 /spl mu/A in a 90 nm process.