Norifumi Kameshiro

Traction inverter that applies compact 3.3 kV / 1200 A SiC hybrid module

A compact 3.3 kV / 1200 A SiC hybrid module which adopts silicon carbide Schottky barrier diodes (SiC-SBDs) and insulated gate bipolar transistors (IGBTs) has been developed. The size of the developed SiC hybrid module is 130 mm × 140 mm, approximately 2/3rd the size of a conventional IGBT module. Using this SiC hybrid module technology, a new traction inverter for railway applications has been developed. The new inverter has been reduced in weight by up to 40% compared to a conventional IGBT inverter. This has been achieved through the use of SiC modules, active gate control technology, reduced cooling system requirements and lightweight oil-free capacitors. The total energy loss of the new inverter is reduced by approximately 35%, through the use of SiC hybrid modules and active gate control drive circuits.

Influence of Lateral Spreading of Implanted Aluminum Ions and Implantation-Induced Defects on Forward Current–Voltage Characteristics of 4H-SiC Junction Barrier Schottky Diodes

Forward current density (J_F)-forward voltage (V_F) characteristics are experimentally and computationally investigated for 4H-silicon carbide junction barrier Schottky (JBS) diodes with a lightly doped (3 - 5 times10¹⁵ cm^-3) drift layer and 2-mum-wide p⁺ stripe regions separated by 1 mum. The J_F-V_F characteristics of fabricated JBS diodes are compared with those of Schottky barrier diodes simultaneously fabricated on the same epitaxial wafers. These J_F-V_F characteristics are also compared with those of simulated JBS diodes, assuming boxlike and Monte Carlo-simulated profiles of aluminum. In the simulation of aluminum ion implantation, concentration contours of created interstitials and vacancies are calculated, and their influence on the J_F-V_F characteristics of JBS diodes is discussed in terms of degradation of electron mobility in the surface region of the drift layer.

Traction inverter that applies hybrid module using 3-kV SiC-SBDs

We have developed SiC-Schottky barrier diodes with a JBS structure that have characteristics of low forward voltage and low leakage current at 3 kV. Further, we have built a prototype of a 3 kV/200 A SiC hybrid module, equipped with Si-IGBTs and SiC-Schottky barrier diodes. We have achieved to reduce the recovery loss and the turn-on loss, by using the SiC hybrid module and a high-speed drive circuit. Moreover, we estimated that the total energy loss of the converter and inverter using the developed SiC hybrid module was reduced to about 30%. Additionally, the inverter succeeded in driving an induction motor for a train.

Electrical Characteristics of Large Chip-Size 3.3 kV SiC-JBS Diodes

The reduction of reverse leakage currents was attempted to fabricate 4H-SiC diodes with large current capacity for high voltage applications. Firstly diodes with Schottky metal of titanium (Ti) with active areas of 2.6 mm2 were fabricated to investigate the mechanisms of reverse leakage currents. The reverse current of a Ti Schottky barrier diode (SBD) is well explained by the tunneling current through the Schottky barrier. Then, the effects of Schottky barrier height and electric field on the reverse currents were investigated. The high Schottky barrier metal of nickel (Ni) effectively reduced the reverse leakage current to 2 x 10-3 times that of the Ti SBD. The suppression of the electric field at the Schottky junction by applying a junction barrier Schottky (JBS) structure reduced the reverse leakage current to 10-2 times that of the Ni SBD. JBS structure with high Schottky barrier metal of Ni was applied to fabricate large chip-size SiC diodes and we achieved 30 A- and 75 A-diodes with low leakage current and high breakdown voltage of 4 kV.

Influence of Trench Structure on Reverse Characteristics of 4H-SiC JBS Diodes

We fabricated trench Junction Barrier Schottky (JBS) diodes, and investigated the effect on the reduction of leakage current and the device yield. First, by calculating of electric field at the Schottky contact interface (Es), we found that the trench JBS structure can reduce Es one digit smaller than the planar JBS structure, setting 80o < The bevel angle θ < 90o. Then, 600 V / 50 A trench JBS diodes are developed and characterized. The leakage current of a trench JBS diode at 600V is 10-2 times smaller than that of planar JBS diode by effectively reducing Es. This enables to reduce the number of low break down samples and raise the yield compared to the planar JBS structure.

Uniform Luminescence at Breakdown in 4H-SiC 4°-Off (0001) p–n Diodes Terminated With an Asymmetrically Spaced Floating-Field Ring

Conventional floating-field rings, which are used to reduce the peak electric field at the periphery of power devices, cause nonuniform avalanche multiplication when applied to planar junctions formed on 4H-SiC substrates misoriented from (0001) toward [1120]. Accordingly, a novel asymmetrically spaced floating-field ring (AS-FFR) was applied to 4H-SiC 4°-off (0001) p-n diodes and found to be effective against such nonuniform avalanche multiplication; that is, luminescence at breakdown was nearly uniform when the spacing between the edge of the anode and the inner edge of the AS-FFR was 2.0 μm in the [1̅1̅20] direction and 1.5 μm in the [112̅0] direction. This result should contribute to exploring the possibility of 4H-SiC power devices with higher avalanche ruggedness.

A Highly Efficient 3.3-kV SiC-Si Hybrid Power Module with a Novel SiC JBS Diode and a Si Advanced Trench HiGT

A 3.3-kV SiC-Si hybrid module, composed of a low-forward-voltage (VF) SiC junction-barrier-Schottky (JBS) diode and a low-saturation-voltage VCE(sat) Si trench IGBT was fabricated and demonstrated highly efficient operation.

SESO memory: A 3T gain cell solution using ultra thin silicon film for dense and low power embedded memories

This work presents a gain-cell solution in which a novel ultrathin poly-silicon film transistor provides the basis for dense and low-power embedded random-access memory. This is made possible by the 2-nm-thick channel of the new transistor (single-electron shut off transistor, or SESO transistor), which realizes a quantum-confinement effect that produces a low leakage current value of only 10/sup -19/ A at room temperature. Combining with vertical SESO structure, 3T gain cell achieves 1/3 the cell area of SRAM. Using circuit techniques, power consumption of SESO memory is expected to be lower than SRAM. The memory has potential to solve the power and stability problem that SRAM is going to face in the near future.

A cavity channel SESO embedded memory with low standby-power techniques

A 22F/sup 2/ 3-transistor dynamic memory cell, based on a newly fabricated cavity channel SESO (single-electron shutoff) transistor is proposed for low-power mobile SOCs. The ultra-low leakage SESO device is formed above the bulk devices to yield the small cell size. With low-power techniques, this memory can achieve nearly an order of magnitude lower standby power than conventional memory. A 1 Mbyte SESO embedded memory core is estimated to have a standby power consumption of 24.2 /spl mu/A in a 90 nm process.