Toshihiko Nishio

Ultrafine-pitch C2 flip chip interconnections with solder-capped Cu pillar bumps

PoP structures have been used widely in digital consumer electronics products such as digital still cameras and mobile phones. However, the final stack height from the top to the bottom package for these structures is higher than that of the current stacked die packages. To reduce the height of the package, a flip chip technology is used. Since the logic chips of mobile applications use a pad pitch of less than 80 µm or less, an ultra-fine-pitch flip chip interconnection technique is required. C4 flip chip technology is widely used in area array flip chip packages, but it is not suitable in the ultrafine-pitch flip chips because the C4 solder bumps melt and collapse on the wide opening Cu pads. Although the industry uses ultrafine-pitch interconnections between Au stud bumps on a chip and Sn/Ag pre-solder on a carrier, this flip chip technique has two major problems. One is that the need for bumps on both die and carrier drives up material costs. The other is that the long bonding process time required in the individual flip chip bonding process with associated heating and cooling steps demands large investments in equipment. To address these problems, we developed the mount and reflow with no-clean flux processes, and new interconnection techniques were developed with Cu pillars and Sn/Ag solder bumps on Al pads for wirebonding, were developed. It is very easy to control the gap between die and substrate by adjusting the Cu pillar height. Since it is unnecessary to control the collapse of the solder bumps, we call this the C2 process for direct Chip Connection (C2). The C2 bumps are connected to Cu substrate pads, which are a surface treated with OSP (Organic Solder Preservative), with reflow and no-clean processes. This technology creates the SMT/Flip Chip hybrid assembly for SoP (System on Package) use. We have produced 50 µm-pitch C2 interconnections and tested their reliability. The interconnection resistance increase caused by the reliability testing is quite small. It is clear that C2 flip chip technology provides robust solder connections at low cost. Also the C2 structure with a low-k device was evaluated and no failures were observed at 1,500 cycles in the thermal cycle test. This indicates that low-k C2 structures seem robust. For finer pitch flip chip interconnections, a wafer-level underfill process is needed to overcome the limitations of the standard capillary underfill process for ultra-narrow spaces. To date, a wafer- level underfill process exists for the C2 process with an 80-µm pitch. In addition to fine pitch interconnections, a die thickness of 70 µm is required to reduce the final stack height. Such thin die cannot be processed by the C2 process because such dies slip too easily during the reflow process. To resolve this issue, a Post-Encapsulation Grinding (PEG) method was developed. In this method the die is ground to less than 70 µm after joining and underfilling. This report presents the PEG method and reliability test results for die thicknesses 20 µm, 70 µm and 150 µm.

Volume visualization of 3D finite element method results

This paper describes a method for visualizing the output data set of a 3D finite element method result. A linear tetrahedral element is used as a primitive for the visualization processing, and a 3D finite element model is subdivided into a set of these primitives, which are generated at every s< îd element. With these primitives, isosurfaces are visualized semltransparentiy from scalar data at each node point. Two methods are developed for the visualization of isosurfaces with and without inteimediate geometries. The methods are applied to output data sets from some simulation results of a semiconductor chip. These are visualized, and the effectiveness of the method is discussed.

Injection molded solder - A new fine pitch substrate bumping method

Injection molded soldering (IMS) technology has been developed for solder bumping of fine-pitch organic substrates. Pure molten solder is injected through a flexible film mask that is aligned to the recessed pad openings to form solder bumps on the substrate. The new substrate bumping method is a simple one pass operation for various size pads, with the capability of forming high solder volume on fine pitch substrate.

Compact modeling approach using genetic algorithms for accurate thermal simulation

We propose a technique that uses thermal measurement results for improved accuracy in thermal simulation of electronic apparatus. Because the modeling of the electronic components in such apparatus has hitherto been very poor, the thermal simulation results cannot achieve the required accuracy. To solve this problem, we first represent a component as a set of cubic blocks with equivalent thermal conductivity and contact thermal resistance values, and then identify these values by using the thermal measurement results for the component. We regard the identification of parameters as an optimization problem that involves minimizing the difference between the predicted and measured results. To solve the problem, we combine genetic algorithms and a thermal simulation tool

A Technique for Developing a Precise Thermal Compact Model

In this paper, we propose a technique to select an appropriate convergence criterion for developing precise thermal compact model. It is known that the compact modeling in thermal simulation can reduce the computing cost for a system level of thermal simulation. We have used the Response Surface Methodology (RSM) to identify parameters of the compact model. However the resulting RSM model is not accurate enough, because the fitness function in thermal simulation has many peak points. We find that this is due to the insufficient convergence of thermal simulation, by investigating temperature results in thermal simulation with the change in thermal conductivities. To solve this problem caused by the insufficient convergence, we optimize the convergence criteria of temperature.Copyright

A compact modeling approach using a genetic algorithm for accurate thermal simulation

The rapid improvement in computer performance is intensifying the component thermal problem. It is becoming increasingly important for an optimal thermal design that thermal simulation is part of the design. Simplification of the thermal simulation model is inevitable as an enormous number of finite elements are required when the original CAD data set is adopted for modeling. However, the reduction of calculation time by model simplification and the maintenance of calculation accuracy are contradictory. Conventionally, model simplification is by empirical judgment, but a rational simplification technique using boundary conditions and material properties results in a more accurate and reliable calculation. Although simplification of the LSI component modeling method has been proposed by the Delphi project, it is difficult to apply other than to components, such as a keyboard. This paper proposes a new technique to generate the compact model of a keyboard with the required accuracy. First, some candidates for the simplified configurations are prepared. A genetic algorithm is proposed to identify the variables such as the boundary conditions and thermal conductivities that are most important in a high accuracy calculation. Finally, the optimum compact model which has the required accuracy is selected from the simplified models.

EP-1500: Development of tumor response observation system for dose-volume delivery guided particle therapy

Results: The measured a photoluminescence peak value of the Gd2O3:Eu was 611nm, which was identical with literature value. In case of the calculated value using GEANT4 montecarlo code, an intensity(counting) of the photoluminescence peak value was 2 times higher, but the peak value also was identical with measured the peak value and overall trend of the photoluminescence spectrum was correspond to the measured data. A result of the decay time showed that the measured value was 1.2 times higher than that of the calculated value despite the higher intensity, but the measured and calculated value was well matched in low intensity.

Material property calculation of interposer card for modeling of Package-on-Package

Package-on-Package(PoP) technology is being used for high density designed and miniaturized electronic applications. In order to develop these small and complicated structured packages, it is important to predict accurately the structural behavior under various thermal conditions. For example, the package warpage control at solder melting temperature is required for the card or sub-package assembly and also the mechanical stress of the joint needs to be taken care of for the jointing reliability. The FEM analysis has been used to understand these behaviors. To get a good model correlation with an actual package, it is most important to use the faithful material property data on the analysis model. On the other hand, if the interposer card is modeled in detail, it must have huge number of mesh and much calculation time is required to solve. The simplified model is preferable to avoid that situation. In general, each interposer card has a different property by application even the package structure to be used is same. The property is calculated to have good accuracy of the rule of mixture (ROM) that can estimate the behavior as a composite material consists of copper wiring, several resins and FR4. In this paper, the ROM was confirmed by measurement with DIC equipment on different circuitry patterned interposer cards, and the behavior dependencies on the wiring density and the warpage are discussed.

MPS-C2 and Post Encapsulation Grinding technology for ultra fine pitch and thin die flip chip applications

Flip chip technology is now being introduced in PoP(Package on Package) packages for the digital consumer electronics such as digital still cameras and mobile phones. PoP reduces the component height and improves the electrical performance. A MPS-C2(Metal Post Solder Chip Connection) method was developed for ultrafine pitch flip chip interconnections in mobile applications. A bare die with Sn/Ag-solder-capped Cu post bumps is directly connected on an organic substrate by using a reflow process without flux cleaning. This technology supports the SMT/Flip Chip-hybrid assembly required for SoP (System on Package) manufacturing, and it is the least expensive method among current ultrafine pitch flip chip interconnetion methods. We ran reliability tests with 50-um-pitch MPS-C2 interconnections. In addition to fine pitch interconnections, each die must be less than 70 um thick to insure that the final stack will be thin enough. Such thin die were not unsuitable for the original MPS-C2 process, because the dies tended to move during the reflow process. We developed a Post Encapsulation Grinding (PEG) method to resolve this problem. In this method the die is ground down to be less than 70 um thick after joining and underfilling.

An approach to reduce build up layers for flip chip-ball grid array (FC-BGA) substrates

Flip Chip-Ball Grid Array (FC-BGA) packages with build-up type organic carriers have been focused towards implementing high I/O counts and electrical performance requirements. Many products utilize 2 build up layers on 2 core layers which is a total of 6 layers with 2-2-2 structure. Three or four build up layers are utilized for higher performance requirements. It is clear that layer count reduction would improve the cost performance for the FC-BGA. This paper shows an approach, using advanced technologies, to reduce 1 build up layer from 2 build up layers product applications of the FC-BGA keeping same I/O counts, electrical performance and reliability. The power plane for simultaneous switching noise, the high speed signal integrity and the structural analysis to compare the warpage and the stress will be applied to confirm the cost performance of the approach.