Yasuharu Yamada

Compact modeling approach using genetic algorithms for accurate thermal simulation

We propose a technique that uses thermal measurement results for improved accuracy in thermal simulation of electronic apparatus. Because the modeling of the electronic components in such apparatus has hitherto been very poor, the thermal simulation results cannot achieve the required accuracy. To solve this problem, we first represent a component as a set of cubic blocks with equivalent thermal conductivity and contact thermal resistance values, and then identify these values by using the thermal measurement results for the component. We regard the identification of parameters as an optimization problem that involves minimizing the difference between the predicted and measured results. To solve the problem, we combine genetic algorithms and a thermal simulation tool

Novel Low Cost Bumping Process with Non-strip Type Photosensitive Resin and Injection Molded Solder (IMS) for Fine Pitch Flip Chip Joining

Fine pitch interconnect is one of key technology elements for 2.5D and 3D IC. Low cost and flexibility in technical aspects are also important, so that the technology can be used for wide range of applications. We have newly developed a non-strip type photosensitive resin and propose a novel IMS bumping process with it for finer pitch flip chip joining in a further cost-effective way. The photosensitive resin layer can be used for IMS bumping Mask and Underfill, and we named the resin layer a Mask and Underfill co-usable layer (MU layer). With this technology, several UBM fabrication methods can be chosen. One of options is electro-less plating after MU layer patterning, and in this case, both solder volume and UBM thickness can be designed flexibly without increasing a risk of UBM bridging as well as solder bridging. In this paper, we present detail results on bumping, bonding, reliability tests with this technology with the MU layer for 80 mm pitch test vehicles. Flip chip joining and temperature cycling reliability were demonstrated with electro-less plated Ni/Au UBM. In addition, we have confirmed that the technology is applicable to 40 μm pitch flip chip joints.

A compact modeling approach using a genetic algorithm for accurate thermal simulation

The rapid improvement in computer performance is intensifying the component thermal problem. It is becoming increasingly important for an optimal thermal design that thermal simulation is part of the design. Simplification of the thermal simulation model is inevitable as an enormous number of finite elements are required when the original CAD data set is adopted for modeling. However, the reduction of calculation time by model simplification and the maintenance of calculation accuracy are contradictory. Conventionally, model simplification is by empirical judgment, but a rational simplification technique using boundary conditions and material properties results in a more accurate and reliable calculation. Although simplification of the LSI component modeling method has been proposed by the Delphi project, it is difficult to apply other than to components, such as a keyboard. This paper proposes a new technique to generate the compact model of a keyboard with the required accuracy. First, some candidates for the simplified configurations are prepared. A genetic algorithm is proposed to identify the variables such as the boundary conditions and thermal conductivities that are most important in a high accuracy calculation. Finally, the optimum compact model which has the required accuracy is selected from the simplified models.

Mechanical properties of Sn-58Bi, In-3Ag and SAC305 solders measured with fine diameter specimens

Lead-free solders such as SnAg or SnAgCu is widely used for flip chip joining. As a result of higher melting temperature and higher elastic modulus of the lead-free solders compared to eutectic SnPb solder, defect of crack or damage in low-k dielectric layers under bond pad for flip chip joining in the semiconductor chip became a serious issue. The crack or damage is caused by mismatch of coefficient of thermal expansion (CTE) between chip and chip carrier substrate after chip join reflow. Various low melting temperature solders have been investigated and proposed as alternatives to SnAg or SnAgCu solders. Mechanical properties including creep properties are important factors as well as melting temperature for stress relief in micro joints and low-k layers. In this paper, the authors report measurement results of creep properties with fine-diameter-specimens (0.5 mm in diameter) of two low melting temperature solders (Sn-58Bi and In-3Ag) and conventional lead-free solder (Sn-3.0Ag-0.5Cu). The measurement matrix consists of four different strain rates and three different temperatures. The stress component n and the constant A in Nortons creep law were derived for each solder alloy.