Koyo Nitta

SuperENC: MPEG-2 video encoder chip

Thanks to increased market acceptance of applications such as digital versatile disks (DVDs), HDTV, and digital satellite broadcasting, the MPEG-2 (Moving Picture Experts Group-2) standard is becoming widely used. The MPEG-2 video standard, established in 1934, provides for a high-quality video compression format that, through high bit rates and frame rates, yields high-resolution video images. Emerging multimedia applications, such as digital versatile disk and high-definition television, demand higher quality video than ever before. In response, our MPEG-2 video encoder chip supports multiple profiles and levels.

Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level

This paper proposes a new architecture for VASA, a single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond the HDTV level, and demonstrates its flexibility and usefulness. This architecture consists of triple encoding cores, a decoding core, a multiplexer/de-multiplexer core, and several dedicated application-specific hardware modules with a hierarchical flexible communication scheme for high-performance data transfer. VASA is the worlds first single-chip full-specs MPEG-2 422P@HL CODEC LSI with a multi-chip configuration. The VASA implements MPEG-2 video and system CODEC with generic audio CODEC interfaces. An LSI incorporating the architecture was successfully fabricated using the 0.13 /spl mu/m eight-metal CMOS process. The architecture not only provides an MPEG-2 422P@HL CODEC but also large scale processing beyond the HDTV level for digital cinema and multi-view/-angled live TV applications with a multi-chip configuration. The VASA implementations will lead to a new dimension in future high-quality, high-resolution digital multimedia entertainment.

An MPEG-2 video encoder LSI with scalability for HDTV based on three-layer cooperative architecture

This paper proposes a new architecture for a single-chip MPEG-2 video encoder with scalability for HDTV and demonstrates its flexibility and usefulness. The architecture based on three-layer cooperation provides flexible data-transfer that improves the encoder from the standpoints of versatility, scalability, and video quality. The LSI was successfully fabricated in a 0.25 /spl mu/m four-metal CMOS process. Its small size and its low power consumption make it ideal for a wide range of applications, such as DVD recorders, PC-card encoders and HDTV encoders.

Development of an HDTV MPEG-2 encoder based on multiple enhanced SDTV encoding LSIs

We have developed a small, low-power HDTV MPEG-2 encoder based on a spatially parallel encoding approach. The encoder consists of multiple enhanced SDTV encoding LSIs, which have already been used to develop a single-chip, low-power MP@ML MPEG-2 video encoder.

Residue role assignment based transform partition predetermination on HEVC

The transform unit (TU), combining with the rate-distortion optimized quantization (RDOQ), as a part of the important features of HEVC brings much performance gain by adding more computation burden to the encoder. Different from the previous standards, the transform and quantization (T&Q) lead into a quadtree structure which requires to be split and calculated recursively for one coding unit (CU). The complexity issues limit the development of both software and hardware video code engine. To solve this problem, this paper proposes a residue role assignment based transform partition predetermination method by introducing the all zero block detection principle. The proposal generates from the observation that the rate-distortion optimized TU partitions generally depend on the distribution of the low frequency residue blocks. 3 different roles are assigned to the residue blocks based on 3 level of residue frequency value. Each role of residue relates to a concrete T&Q calculation. Therefore, instead of traversal calculating of full T&Q size and T&Q depth, the residue blocks are categorized previously and only the corresponding T&Q are calculated. The evaluation results state that the proposal can achieve 12.8% and 26.3% total encoding time reduction with only 1.00% and 0.80% BD bit-rate loss in average with both RDOQ off and on cases.

An H.264/AVC High422 profile and MPEG-2 422 profile encoder LSI for HDTV broadcasting infrastructures

An H.264/AVC encoder LSI (named SARA/E) that supports High422 profile, as well as 422 profile of MPEG-2, has been developed for HDTV broadcasting infrastructures. It contains 257GOPS motion estimation and compensation (ME/MC) engines with search ranges of -271.75 to +199.75 (H) /-109.75 to +145.75 (V), which can utilize almost all H.264/AVC ME/MC tools, multiple reference frame, variable block size, 1/4-pel prediction, macroblock adaptive field/frame prediction, temporal/spatial direct mode, and weighted prediction. Our evaluations show that it can encode fast moving scenes with 1.2 to 1.7 dB higher than the JM. It was successfully fabricated in a 90 nm 9level metal CMOS technology. It integrates 140 million transistors.

Motion-estimation/motion-compensation hardware architecture for a scene-adaptive algorithm on a single-chip MPEG-2 MP@ML video encoder

This paper proposes a unique motion estimation and motion compensation (ME/MC) hardware architecture for a scene- adaptive algorithm. The most significant feature is the independence of the two modules for the ME/MC. This enables the encoder to analyze the statistics of a scene before encoding it and to control the whole encoding process adaptively according to the scene. The scene-adaptive controls involve changing various encoding parameters, such as the search area or selection criteria, in the slice cycle or even in the macroblock cycle. The search area of our ME/MC architecture is plus or minus 211.5 horizontally and plus or minus 113.5 vertically by the area hopping method. The architecture is loaded on a single-chip MPEG2 MPML encoder.

MVC real-time video encoder for full-HDTV 3D video

3D video technologies such as 3D cameras, displays, and video-processing have become more important for achieving high quality and immersive video services. We propose an H.264 MVC encoder architecture for real-time 3D video distribution and transmission. We also present the first-ever successful development of a full-HDTV real-time MVC encoder.

Single-chip 4K 60fps 4:2:2 HEVC video encoder LSI with 8K scalability

This paper proposes the worlds first single-chip 4K 60fps 4:2:2 HEVC video encoder LSI (named “NARA”) with 8K scalability for broadcasting with professional high image quality. It consists of a prediction core with a new prediction mode decision framework, dual coding cores, controlling RISCs, and high speed data buses with multichip 8K configuration, using 28nm CMOS technology. The NARA LSI will lead to a new dimension in future high-quality 8K world.

Professional H.264/AVC CODEC chip-set for high-quality HDTV broadcast infrastructure and high-end flexible CODEC systems

This article consists of a collection of slides from the authors conference presentation on NTTs H.264/AVC CODEC chip-set for high quality HDTV broadcast infrastructures and high end flexible CODEC systems. Some of the specific topics discussed include: the special features of NTTs video CODEC chips; system specifications, and system design for these products; system architectures; applications for use; platforms supported; processing capabilities; chip implementations; SARA chip deployment; and targeted markets.