Toshihiro Terazawa

A 60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

This MPEG4 video codec implements essential functions in the MPEG4 committee draft. It consumes 60 mW at 30 MHz, 30% of the power dissipation of a conventional CMOS design. Measured power dissipation is summarized. 70% power reduction is achieved by low-power techniques at circuit and architectural levels. A 16b RISC processor provides software programmability. Binary shape decoding uses 20% of the computation power of the RISC processor at 30MHz clock, with negligible increase in chip power dissipation. Three-step hierarchical motion estimation reduces power dissipation.

A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme

A novel design technique which combines a variable supply-voltage scheme and a clustered voltage scaling is presented (VS-CVS scheme). A theory to choose the optimum supply voltages in the VS-CVS scheme is discussed which enables us to perform chip design in a top-down fashion. Level-shifting flip-flops are developed which reduce power, delay and area penalties significantly. Application of this technique to an MPEG4 video codec saves 55% of the power dissipation without degrading circuit performance compared to a conventional CMOS design.

A 60 MHz 240 mW MPEG-4 video-phone LSI with 16 Mb embedded DRAM

A 240 mW single-chip MPEG-4 video-phone LSI with a 16 Mb embedded DRAM is fabricated in a 0.25 /spl mu/m CMOS, triple-well, quad-metal technology. The chip integrates a 16 Mb DRAM and three dedicated 16 b RISC processors with dedicated hardware accelerators that serve as an MPEG-4 video codec, a speech codec, and a multiplexer. It also integrates camera, display, and audio interfaces required for a video-phone system. It consumes 240 mW at 60 MHz operation, which is only 22% of the power dissipation of a conventional design. A variable threshold voltage CMOS (VTCMOS) technology is employed to reduce standby leakage current to 26 /spl mu/A, which is only 17% of the conventional CMOS design.

Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques

This paper describes a fully automated low-power design methodology in which three different voltage-scaling techniques are combined together. Supply voltage is scaled globally, selectively, and adaptively while keeping the performance. This methodology enabled us to design an MPEG4 codec core with 58% less power than the original in three week turn-around-time.

A 160 mW, 80 nA standby, MPEG-4 audiovisual LSI with 16 Mb embedded DRAM and a 5 GOPS adaptive post filter

A single-chip MPEG-4 audiovisual LSI in a 0.13 /spl mu/m 5M CMOS technology with 16 Mb embedded DRAM is presented. Four 16 b RISC processors and dedicated hardware accelerators including a 5 GOPS post filtering engine are integrated on the IC. The chip consumes 160 mW at 125 MHz and uses 80 nA in the standby mode. This LSI handles MPEG-4 CIF video encoding at 15 frames/s and audio encoding simultaneously.

Flip-flop selection technique for power-delay trade-off [video codec]

Circuit and design techniques trade off power, delay, and area of a chip by blending different types of flip-flops with different merits: F/F blending. Three types of discrete cosine transform (DCT) blocks for MPEG-4 video codec, a conventional design (Conv-DCT), a low-power design (LP-DCT), and a high-speed design (HS-DCT), are fabricated in a 0.3 /spl mu/m CMOS technology. LP-DCT consumes 24%-51% less power without speed degradation, and HS-DCT operates 25% faster than Conv-DCT.

A scalable MPEG-4 video codec architecture for IMT-2000 multimedia applications

A scalable MPEG-4 video codec architecture is proposed to achieve low power consumption and high cost-effectiveness for IMT-2000 multimedia applications. The MPEG-4 video codec consists of a 16-bit multimedia-extended RISC processor and dedicated hardware accelerators, which bring about both low power consumption and programmability. The proposed architecture is extended and applied for the development of two MPEG-4 LSIs. One is an MPEG-4 video codec LSI, which performs an MPEG-4 video encoding and decoding at 15 frames per second with quarter common intermediate format. The other is an MPEG-4 audiovisual LSI, containing three 16-bit RISC processors and a 16-Mbit embedded DRAM, executes the major functions of 3GPP 3G-324M video telephony for IMT-2000 applications. By introducing the optimization of the embedded DRAM configuration, clock gating technique, and low power motion estimation, the MPEG-4 audiovisual LSI consumes only 240 mW when it activates MPEG-4 video SP@L1 codec, the AMR speech codec, and the H.223 annex B multiplex at 60 MHz clock rate.