Toshikazu Fukuda

Measurement of neutron-induced single event transient pulse width narrower than 100ps

A novel SET pulse measurement circuit is proposed which can detect pulses narrower than 100ps. Alternation of SET pulses during the propagation through the chain of target cells is minimized, which is attributed to small chain length (typically 20). This circuit configuration contributes to obtaining pulse distribution similar to that observed in actual circuit in use. Distribution of SET pulse width measured by our circuit through the white neutron beam testing agrees well with that estimated by computer simulation.

13.4 A 7ns-access-time 25μW/MHz 128kb SRAM for low-power fast wake-up MCU in 65nm CMOS with 27fA/b retention current

Battery lifetime is the key feature in the growing markets of sensor networks and energy-management system (EMS). Low-power MCUs are widely used in these systems. For these applications, standby power, as well as active power, is important contributor to the total energy consumption because active sensing or computing phases are much shorter than the standby state. Figure 13.4.1 shows a typical power profile of low-power MCU applications. To achieve many years of battery lifetime, the power consumption of the chip must be kept below 1μA during deep sleep mode. Another key feature of a low-power MCU for such applications is fast wake-up from deep-sleep mode, which is important for low application latency and to keep wake-up energy minimal. For fast wake-up, the system must retain its state and logged information during sleep mode because several-hundred microseconds are needed for reloading such data to memories. Conventional SRAM consumes much higher retention current than the required deep-sleep-mode current as shown in Fig. 13.4.1. Embedded Flash memories have limited write endurance on the order of 105 cycles making them difficult to use in applications that frequently power down. Embedded FRAM [1,2] has been used for this purpose and it could be used as a random-access memory as well as a nonvolatile memory. However, as a random-access memory, its slow operation and high energy consumption [1,2] limits performance of the MCU and battery lifetime. Furthermore, additional process steps for fabricating FRAM memory cells increase the cost of MCU. SRAM can operate at higher speed with lower energy without additional process steps, but high retention current makes it difficult to sustain data in deep-sleep mode. To solve this problem, we develop low-leakage current SRAM (XLL SRAM) that reduce retention current by 1000× compared to conventional SRAM and operate with less than 10ns access time. The retention current of XLL SRAM is negligible in the deep-sleep mode because it is much smaller than the amount of the deep-sleep-mode current of MCU, which is dominated by active current of the real-time clock and control logic circuits. By using XLL SRAM, the store and reload process during mode transitions can be eliminated and wake-up time from deep-sleep mode of MCU is reduced to few microseconds. This paper describes a 128kb SRAM with 3.5nA (27fA/b) retention current, 7ns access time, and 25μW/MHz active energy consumption. Its low retention current, high-speed, and low-power operation enable to activate SRAM in the deep-sleep mode, and also provides fast wake-up, low active energy consumption and high performance to MCU.

Scaling effect and circuit type dependence of neutron induced single event transient

Neutron induced single event transient (SET) has been measured on NAND and inverter (INV) chain with changing fan-out, drive strength, size of drain diffusion area, temperature and VDD on 40nm and 90nm bulk CMOS technology. As the pulse width distribution varies with the length of SET target chain as well, it is important to use the chain length similar with the actual logic circuits. Using tens of stages of target chain, pulses wider than 150ps have been rarely observed. The results of the measurement show that the SER of SET changes depending on the cell type and fan-out. SER of SET in combinational logic circuits decreases by half from 90nm to 40nm for the same gate count and the same clock frequency.

Study on Influence of Device Structure Dimensions and Profiles on Charge Collection Current Causing SET Pulse Leading to Soft Errors in Logic Circuits

Current responses due to the strike of ionized particle onto nMOS transistor of 90nm and 55nm generation have been analyzed through 3D device simulations. From the current response, duration of charge collection (tcc) is determined, which correlated strongly with the width of erroneous pulse (SET pulse). Causes of the difference between tcc values of 90nm and 55nm generation MOSFETs have been investigated and it is found that the difference in STI depth and width of p-well contact line between these two generations influences tcc mainly. This is because that the resistance below the p-well contact affects the ability to pull out the excess holes remaining in the channel region. It is also shown that there is room for reducing tcc and hence SET pulse width by well profile engineering. I. INTRODUCTION Neutron-induced soft error phenomena have received much attention since they are considered as one of the major ob- stacles to realize highly reliable LSIs. Although Single-Event- Upset observed in memory circuits such as SRAMs and flip- flops is still major concern, soft error phenomena occurring in combinational-logic circuits can be more serious in future technology node (1). In the logic circuits, propagation of erroneous signal, called Single-Event-Transient (SET), occurs and the erroneous signal might be finally stored, for instance, in a flip-flop as illustrated in Fig. 1. The wider the SET pulse is, the more probably the erroneous signal is stored. Such a SET pulse is initially caused by collection of generated charge due to the impact of the ionized particle. In this paper, duration of charge collection is evaluated which is related to SET pulse width strongly, and its dependence on device structure dimensions and profiles is investigated.

Alpha and Neutron SER of embedded-SRAM and Novel Estimation Method

Alpha and neutron SERs of embedded-SRAMs are evaluated. From the results for several technology generations, SER is expressed as a function of diffusion area and critical charge for devices, but the effect of collection efficiency is constant for the generations. Then, the technology independent SER model named universal curve is introduced. Moreover, SER trend to 45nm generation is quantitatively estimated based on the future trend of device technology