Taiki Uemura

SEILA: Soft error immune latch for mitigating multi-node-SEU and local-clock-SET

We have developed a robust latch for achieving high reliability in LSI. The latch can attenuate multi-node single-event-upset (MNSEU) and single event transient on local-clock (SETLC). The robust latch has Dual-clock-buffers (DCB) and Double-height-cell (DHC) technologies. Results on neutron acceleration experiments show that DHC can dramatically attenuate MNSEU and DCB can protect almost SETLC of the latch. In addition, we investigate optimum design in well structure.

Neutron-induced soft-error simulation technology for logic circuits

In this paper, we describe the simulation technology used to estimate soft errors in logic circuits. The neutron induced soft-error simulator (NISES), which was previously developed for estimating soft-errors in memories is applied to the estimating soft errors in latch circuits and its effectiveness is shown. We model soft-error phenomena in combinational circuits and develop a novel simulation system for estimating soft errors in such circuits. Estimated results show that soft-error rate increases in combinational circuits as technology advances. Soft errors in logic circuits will thus become crucial.

Measurement of neutron-induced single event transient pulse width narrower than 100ps

A novel SET pulse measurement circuit is proposed which can detect pulses narrower than 100ps. Alternation of SET pulses during the propagation through the chain of target cells is minimized, which is attributed to small chain length (typically 20). This circuit configuration contributes to obtaining pulse distribution similar to that observed in actual circuit in use. Distribution of SET pulse width measured by our circuit through the white neutron beam testing agrees well with that estimated by computer simulation.

Using Low Pass Filters in Mitigation Techniques against Single-Event Transients in 45nm Technology LSIs

In this paper, we investigate optimum radiation hardened by design (RHBD) for use against single-event transients (SET) using low-pass filters (LPF) including RHBD techniques against single-event upsets (SEU) for sequential logic in 45 -nm technology in a terrestrial environment. Three types of LPF were investigated regarding their SET pulse immunities, area penalties, and performance penalties. We proposed a flip-flop of SET-SEU-RHBD. This flip-flop has LPF using a C-element with dual transmission and applies an MNL technique only on the master latch. This flip-flop is designed with 45-nm technology and a 16-grid height. Mitigation efficiencies of the flip-flop are estimated by accelerated experiments and simulations. The flip-flop can protect 90% of SEU and 52 ps SET pulse with low penalties.

Scaling effect and circuit type dependence of neutron induced single event transient

Neutron induced single event transient (SET) has been measured on NAND and inverter (INV) chain with changing fan-out, drive strength, size of drain diffusion area, temperature and VDD on 40nm and 90nm bulk CMOS technology. As the pulse width distribution varies with the length of SET target chain as well, it is important to use the chain length similar with the actual logic circuits. Using tens of stages of target chain, pulses wider than 150ps have been rarely observed. The results of the measurement show that the SER of SET changes depending on the cell type and fan-out. SER of SET in combinational logic circuits decreases by half from 90nm to 40nm for the same gate count and the same clock frequency.

Simultaneous measurement of soft error rate of 90 nm CMOS SRAM and cosmic ray neutron spectra at the summit of Mauna Kea

We carried out simultaneous measurement of SERs and cosmic ray neutron spectra for the first time. We measured SERs using 90 nm CMOS SRAM chips and measured neutron spectra using a Bonner multisphere spectrometer. We carried out the SER field measurement at the 4200 m summit of Mauna Kea, which is the most suitable place for SER field measurements because the neutron flux is over 10 times greater there than that at sea level. Therefore, we could avoid making field measurements that usually require a long measuring time (about a year) to obtain sufficient accuracy.

The 10th Generation 16-Core SPARC64™ Processor for Mission Critical UNIX Server

The 10th generation SPARC64™ processor named SPARC64 X contains 3-billion transistors on a 588mm2 die fabricated in an enhanced 28nm high-κ metal-gate (HKMG) CMOS process, with 13 layers of copper interconnect with low-κ dielectrics. More stress control, SiGe improvement and S/D optimization achieve about 10% higher performance than the standard 28nm high performance (28HP) process. SPARC64 X runs at 3.0GHz and consists of 16 cores, shared 24MB level 2 (L2) cache, four channels of 1.6GHz DDR3 controller, two ports of PCIe Gen3 controller, and five ports of system interface controller. ccNUMA is adopted as its memory system, and a cache coherence control unit for multi-chip systems with up to 64 processors is integrated into L2 cache control circuitry for lower latency and reduced area and power consumption.

Investigation of multi cell upset in sequential logic and validity of redundancy technique

Purpose of this work is investigation of validity on redundancy techniques for soft-error mitigation in sequential elements such as flop-flops and latches. We have evaluated multi-cell-upset (MCU) in sequential elements through neutron acceleration experiments at Osaka Univ. We have calculated mitigation efficiency of the redundancy technique from the experimental results. MCU ratio increases with technology advancing. Validity of the redundancy technique is kept even on advanced technologies.

Neutron-induced soft error analysis in MOSFETs from a 65nm to a 25 nm design rule using multi-scale Monte Carlo simulation method

We have analyzed terrestrial neutron-induced soft errors in MOSFETs from a 65 nm to a 25 nm design rule by means of multi-scale Monte Carlo simulation using PHITS-HyENEXSS code system. The resulting scaling trend of SERs per bit is still decreasing similar to other predictions. From this analysis, it is clarified that secondary He and H ions provide a major impact on soft errors with decreasing critical charge. It is also found that terrestrial neutrons with energies up to several hundreds of MeV have a significant contribution to soft errors regardless of design rule and critical charge.

Study on Influence of Device Structure Dimensions and Profiles on Charge Collection Current Causing SET Pulse Leading to Soft Errors in Logic Circuits

Current responses due to the strike of ionized particle onto nMOS transistor of 90nm and 55nm generation have been analyzed through 3D device simulations. From the current response, duration of charge collection (tcc) is determined, which correlated strongly with the width of erroneous pulse (SET pulse). Causes of the difference between tcc values of 90nm and 55nm generation MOSFETs have been investigated and it is found that the difference in STI depth and width of p-well contact line between these two generations influences tcc mainly. This is because that the resistance below the p-well contact affects the ability to pull out the excess holes remaining in the channel region. It is also shown that there is room for reducing tcc and hence SET pulse width by well profile engineering. I. INTRODUCTION Neutron-induced soft error phenomena have received much attention since they are considered as one of the major ob- stacles to realize highly reliable LSIs. Although Single-Event- Upset observed in memory circuits such as SRAMs and flip- flops is still major concern, soft error phenomena occurring in combinational-logic circuits can be more serious in future technology node (1). In the logic circuits, propagation of erroneous signal, called Single-Event-Transient (SET), occurs and the erroneous signal might be finally stored, for instance, in a flip-flop as illustrated in Fig. 1. The wider the SET pulse is, the more probably the erroneous signal is stored. Such a SET pulse is initially caused by collection of generated charge due to the impact of the ionized particle. In this paper, duration of charge collection is evaluated which is related to SET pulse width strongly, and its dependence on device structure dimensions and profiles is investigated.