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Dive into the research topics where Toshinori Hosokawa is active.

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Featured researches published by Toshinori Hosokawa.


asian test symposium | 1998

An optimal time expansion model based on combinational ATPG for RT level circuits

Tomoo Inoue; Toshinori Hosokawa; Takahiro Mihara; Hideo Fujiwara

We present an approach to test generation using time expansion models. The tests for acyclic sequential circuits can be generated by applying combinational ATPG to our time expansion models. We performed experiments on application to partial scan designed register-transfer circuits. The results show that our approach can reduce hardware overhead and test length compared with full scan while preserving almost 100% fault efficiency.


asian test symposium | 2002

A test point insertion method to reduce the number of test patterns

Masayoshi Yoshimura; Toshinori Hosokawa; Mitsuyasu Ohta

The recent advances in semiconductor integration technology have resulted in an increasing number of the test lengths of full scan designed LSI. This paper presents a test point insertion method for reducing test patterns of full scan designed LSI. In our method, test points are inserted based on improved fault detection probability and value assignment probability such that test patterns are efficiently compacted. Experimental results for some practical designs show that the rate of test pattern compaction ranges from 31% to 65%. Those results also prove that our method is very effective for reducing the number of test patterns.


asia and south pacific design automation conference | 2003

VCore-based design methodology

Michiaki Muraoka; Hideyuki Hamada; Hiroaki Nishi; Toshihiko Tada; Yoichi Onishi; Toshinori Hosokawa; Kenji Yoshida

The VCore [1](*) based design methodology, which has been developed at the VCDS (**) Project, is a SoC design methodology using VCores. A VCore is a reusable, high level abstracted design component. We have developed the VCore based design methodology and the VCDS tool prototype. We used the developed tool and did a trial SoC design. The design result showed that SoC design productivity improved using the proposed methodology.VCDS: Virtual Core based Design SystemVCore: Virtual Core


asia and south pacific design automation conference | 1995

Design for testability using register-transfer level partial scan selection

Akira Motohara; Sadami Takeoka; Toshinori Hosokawa; Mitsuyasu Ohta; Yuji Takai; Michihiro Matsumoto; Michiaki Muraoka

An approach to top down design for testability using register-transfer level (RTL) partial scan selection is described. We propose a scan selection technique based on testability analysis for RTL design including data path circuits and control circuits such as state machines. Registers and state machines which make gate level ATPG difficult are identified by the scan selection technique based on RTL testability analysis effectively. Experimental results for actual circuits are also presented.


asia and south pacific design automation conference | 2001

Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times

Toshinori Hosokawa; Masayoshi Yoshimura; Mitsuyasu Ohta

As an LSI is on the two-dimensional plane, the number of external pins of an LSI does not equally increase to the number of gates. Therefore, the number of flip-flops on a scan path is relatively increasing. As the results, the test application time becomes longer. In this paper, three new DFT strategies are proposed to reduce the test application time. Experimental results showed the DFT strategies reduced the test application times by 46 to 82% compared with a conventional full scan design method.


asian test symposium | 1997

A partial scan design method based on n-fold line-up structures

Toshinori Hosokawa; Toshihiro Hiraoka; Mitsuyasu Ohta; Michiaki Muraoka; Shigeo Kuninobu

We will present a partial scan design method based on n-fold line-up structures and a partial scan design method based on the state justification of pure FFs of load/hold type in order to achieve high fault efficiency for practical LSIs. We will also present a dynamic test sequence compaction method for acyclic structures. Experimental results for practical LSIs show that our presented methods can achieve high fault efficiency and reduce the number of test patterns by half.


asian test symposium | 1996

A design for testability method using RTL partitioning

Toshinori Hosokawa; Kenichi Kawaguchi; Mitsuyasu Ohta; Michiaki Muraoka

We will present a Design For Testability (DFT) method on Register Transfer Level (RTL). In our method RTL circuits are partitioned into some testable blocks, and each of the blocks is isolated by using primary pins and additional multiplexers so that automatic test pattern generation (ATPG) can be applied for each of the blocks. The experimental results for some RTL circuits designed with Bchart show that our method reduces the number of test patterns from a seventeenth to an eightieth and 10 to 30% of area overhead for test circuits in comparison with a full scan design method.


vlsi test symposium | 2002

A test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits

Toshinori Hosokawa; Hiroshi Date; Michiaki Muraoka

This paper proposes a test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits with DFT where hierarchical test generations are applicable. Moreover, a heuristic algorithm for a compacted test plan table generation is proposed. The proposed methods could shorten test lengths for some RTL data path circuits compared with the conventional hierarchical test generation method.


asian test symposium | 2002

A SoC test strategy based on a non-scan DFT method

Hiroshi Date; Toshinori Hosokawa; Michiaki Muraoka

This paper proposes a system-on-a-chip (SoC) test strategy based on a non-scan DFT method. Especially, we evaluate a basic DFT method, called NS-DFT, comparing it with a full scan DFT method. The experimental results for practical circuits and benchmark circuits demonstrate the efficiency of the NS-DFT.


european test symposium | 2015

A low capture power test generation method using capture safe test vectors

Atsushi Hirai; Yukari Yamauchi; Toshinori Hosokawa; Masayuki Arai

In this paper, we propose a new low capture power test generation method based on fault simulation to reduce the number of unsafe faults. The method uses capture-safe test vectors in an initial test set to generate new test vectors. Our experimental results show that the use of this method reduces the number of unsafe faults by 94% on average, and while requiring less test generation time compared with the conventional low capture power test generation method.

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Hideo Fujiwara

Nara Institute of Science and Technology

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Hiroshi Yamazaki

College of Industrial Technology

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Tomoo Inoue

Hiroshima City University

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Masayuki Arai

College of Industrial Technology

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