Michiaki Muraoka

VCore-based design methodology

The VCore [1](*) based design methodology, which has been developed at the VCDS (**) Project, is a SoC design methodology using VCores. A VCore is a reusable, high level abstracted design component. We have developed the VCore based design methodology and the VCDS tool prototype. We used the developed tool and did a trial SoC design. The design result showed that SoC design productivity improved using the proposed methodology.VCDS: Virtual Core based Design SystemVCore: Virtual Core

Design for testability using register-transfer level partial scan selection

An approach to top down design for testability using register-transfer level (RTL) partial scan selection is described. We propose a scan selection technique based on testability analysis for RTL design including data path circuits and control circuits such as state machines. Registers and state machines which make gate level ATPG difficult are identified by the scan selection technique based on RTL testability analysis effectively. Experimental results for actual circuits are also presented.

A partial scan design method based on n-fold line-up structures

We will present a partial scan design method based on n-fold line-up structures and a partial scan design method based on the state justification of pure FFs of load/hold type in order to achieve high fault efficiency for practical LSIs. We will also present a dynamic test sequence compaction method for acyclic structures. Experimental results for practical LSIs show that our presented methods can achieve high fault efficiency and reduce the number of test patterns by half.

A design for testability method using RTL partitioning

We will present a Design For Testability (DFT) method on Register Transfer Level (RTL). In our method RTL circuits are partitioned into some testable blocks, and each of the blocks is isolated by using primary pins and additional multiplexers so that automatic test pattern generation (ATPG) can be applied for each of the blocks. The experimental results for some RTL circuits designed with Bchart show that our method reduces the number of test patterns from a seventeenth to an eightieth and 10 to 30% of area overhead for test circuits in comparison with a full scan design method.

A test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits

This paper proposes a test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits with DFT where hierarchical test generations are applicable. Moreover, a heuristic algorithm for a compacted test plan table generation is proposed. The proposed methods could shorten test lengths for some RTL data path circuits compared with the conventional hierarchical test generation method.

Synthesis for SoC architecture using VCores

In this paper, we propose a novel architecture synthesis method for SoC using VCores. VCores are reusable and configurable high-level descriptions. An initial SoC architecture, which consists of a CPU, buses, and peripherals, is generated based on an architecture template. The hardware and software tradeoff is possible on the architecture model after assignment of software VCores or hardware VCores. The assignment is based on the results of the architectures performance estimation. We present a prototype of the synthesis for SoC architecture using VCores and an architecture level design experiment using this prototype.

A SoC test strategy based on a non-scan DFT method

This paper proposes a system-on-a-chip (SoC) test strategy based on a non-scan DFT method. Especially, we evaluate a basic DFT method, called NS-DFT, comparing it with a full scan DFT method. The experimental results for practical circuits and benchmark circuits demonstrate the efficiency of the NS-DFT.

A RTL partitioning method with a fast min-cut improvement algorithm

A design flow with register transfer level (RTL) partitioning and an RTL partitioning algorithm for efficient logic synthesis and layout are described in this paper. By changing the parameter of the partitioning optimization dynamically, the algorithm improves the interconnection cost in a short CPU time. Experimental results on large circuits show that the algorithm partitioned circuits with a large number of RTL components in 1/10 to 1/100 of conventional partitioning times.

Design methodology for SoC architectures based on reusable virtual cores

The design reuse methodology, which has been developed at the VCDS Project, is a SoC design methodology to reduce the SoC design time using high level design intellectual properties named as Virtual Cores (VCores). In this paper, we propose the VCore based design methodology to synthesize the SoC architecture from the system level specification. This synthesis methodology generates an initial architecture that consists of a CPU, buses, I/Os peripherals, and RTOS (Real Time Operating System), and makes tradeoffs between hardware and software on assigned software VCores and hardware Vcores models to the architecture. The results of an architecture level design experiment using the proposed methodology shows that the partial automation of the communication refinement process, allied with design reuse, accelerates the architecture synthesis, thus reducing the design time required to design an architecture.

VCDS tool demonstration

The VCore(*) based Design Methodology developed in the VCDS(**) project is a novel design methodology utilizing VCores. VCores are reusable functional cores defined at high level. We designed a SoC for Wearable Computer as a vehicle application in the pilot project (Figure 1), and compared our proposed methodology with a conventional RTL based design methodology by measuring the design productivity. We obtained very promising prospects that the design productivity could be improved 20 times for the enhanced VCDS (Figure 2).We will make a demonstration of the implemented pilot tool to show how effective our proposed methodology is.(*) VCore: Virtual Core(**) VCDS: Virtual Core based Design System