Mitsuyasu Ohta

A test point insertion method to reduce the number of test patterns

The recent advances in semiconductor integration technology have resulted in an increasing number of the test lengths of full scan designed LSI. This paper presents a test point insertion method for reducing test patterns of full scan designed LSI. In our method, test points are inserted based on improved fault detection probability and value assignment probability such that test patterns are efficiently compacted. Experimental results for some practical designs show that the rate of test pattern compaction ranges from 31% to 65%. Those results also prove that our method is very effective for reducing the number of test patterns.

On validating data hold times for flip-flops in sequential circuits

We consider the problem of validating flip-flop data hold time requirements in sequential circuits. The data hold time violations considered are related to the presence of short paths that allow changes in next-state values to occur fast enough so as to cause latching of erroneous next-states. Three fault models are proposed that are related to the presence of short paths in the circuit. Propagation conditions for robust and non-robust tests for short paths are given. A test generation procedure is described for one of the proposed models, and experimental results are provided for benchmark circuits.

Design for testability using register-transfer level partial scan selection

An approach to top down design for testability using register-transfer level (RTL) partial scan selection is described. We propose a scan selection technique based on testability analysis for RTL design including data path circuits and control circuits such as state machines. Registers and state machines which make gate level ATPG difficult are identified by the scan selection technique based on RTL testability analysis effectively. Experimental results for actual circuits are also presented.

Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times

As an LSI is on the two-dimensional plane, the number of external pins of an LSI does not equally increase to the number of gates. Therefore, the number of flip-flops on a scan path is relatively increasing. As the results, the test application time becomes longer. In this paper, three new DFT strategies are proposed to reduce the test application time. Experimental results showed the DFT strategies reduced the test application times by 46 to 82% compared with a conventional full scan design method.

A partial scan design method based on n-fold line-up structures

We will present a partial scan design method based on n-fold line-up structures and a partial scan design method based on the state justification of pure FFs of load/hold type in order to achieve high fault efficiency for practical LSIs. We will also present a dynamic test sequence compaction method for acyclic structures. Experimental results for practical LSIs show that our presented methods can achieve high fault efficiency and reduce the number of test patterns by half.

A design for testability method using RTL partitioning

We will present a Design For Testability (DFT) method on Register Transfer Level (RTL). In our method RTL circuits are partitioned into some testable blocks, and each of the blocks is isolated by using primary pins and additional multiplexers so that automatic test pattern generation (ATPG) can be applied for each of the blocks. The experimental results for some RTL circuits designed with Bchart show that our method reduces the number of test patterns from a seventeenth to an eightieth and 10 to 30% of area overhead for test circuits in comparison with a full scan design method.

A new inter-core built-in-self-test circuit for tri-state buffers in the system-on-a-chip

A new inter-core BIST circuit for tri-state buffers, T-BIST, mainly consists of simple circuits distributed in the relevant blocks. It can give an excellent test-coverage with a little additional hardware. Its configuration is not specified by each SoC structure, so it is suitable for a general/reusable testable IP.