Toshiro Akino

A new layout synthesis for leaf cell design

We propose a new layout synthesis with 2 dimensional transistor arrangement and a spontaneous process of 2 dimensional compaction and local re routing. The compaction enables jumping over objects, minimizing the number of contacts for wiring. We applied the layout synthesis to actual cell design and obtained comparable results to hand crafted design.

A two-dimensional transistor placement for cell synthesis

Proposes a transistor placement algorithm to generate standard cell layout in a 2D placement style that is not restricted to row-based transistor placement. The cost function constructed for transistor placement optimization is able to optimize wirings directly and diffusion sharing indirectly but sufficiently. This transistor placement algorithm, applied to several standard cells, has demonstrated the capability to generate a nearly-optimal 2D placement that is comparable to manually designed placement.

A new approach of fractal-dimension based module clustering for VLSI layout

This paper describes a new clustering approach for VLSI placement, which is based on a fractal dimension analysis for the topological structure of modules in a logic diagram. A distinctive feature of this approach is that the concept of a fractal dimension has been introduced into a logic diagram in such a way that clustering of modules is iterated while the fractal dimension of clustered modules remains in a prescribed range. A part of experimental results is also shown, which demonstrates that our clustering approach achieves better solutions than the conventional placement without clustering.<<ETX>>

A high-speed domino CMOS full adder driven by a new unified-BiCMOS inverter

A new operation mode using a partially depleted hybrid lateral BJT-CMOS inverter on SOI, named as unified-BiCMOS (U-BiCMOS) inverter, is proposed. The scheme utilizes the gated lateral npn or pnp BJT inherent of nor p-channel MOSFETs. Forward current is applied to the base terminal of the channel MOSFETs, with a normal pull-up or pull-down MOSFET as a current source, where each drain terminal is connected to the corresponding base terminal of the inverter. A logic scheme is also proposed to control the gates of the pull-up or pull-down MOSFETs in switching states using output signals made from two CMOS inverters with different resistance ratios. Circuit simulation using 0.35 /spl mu/m BSIM3v3 model parameters for MOSFETs and a current gain of /spl beta//sub F/=100 for BJTs, shows the speed of a domino CMOS full adder with the U-BiCMOS inverter (DCFAU) to be 1.9 times faster than that of a static CMOS full adder with 3-stage CMOS inverter (SCFA3S) designed on the basis of logical effort for driving a load capacitance of 0.3542 pF at V/sub dd/=1.2 V. The energy consumption of the DCFAU is also approximately 20% lower than that of the SCFA3S.