Toshiya Akamatsu

Study of Chip Stacking Process and Electrical Characteristic Evaluation of Cu Pillar Joint Between Chips Including TSV

Three-dimensional chip stacking is a useful integration technology for improving electrical performance. In this study, we manufactured two different-sized stacked chips and examined the stacking process and electrical properties of a Cu pillar joint with a through-silicon via (TSV). To achieve alignment accuracy, a stacking process using reflow with reduction atmosphere was evaluated. As a result, the reflow process ensured bonding accuracy and the successful joining of a CuSn intermetallic compound. To determine electrical characteristics, we evaluated the electro-migration of the Cu pillar intermetallic compound (IMC) joint, which resulted in problems with small inter-chip connection. It was clarified that there was no damage to the TSV or TSV joint from the current flow, and the lifetime of the Cu pillar joint constructed with a CuSn IMC was determined to have improved by several times compared with a conventional Cu pillar and a solder joint.

Reliability studies on micro-joints for 3D-stacked chip

Three-dimensional chip stacking technology is expected to be a powerful method for achieving a short wiring distance between chips, and high-density integration of the functions in the chip, and to achieve the next generations high-performance large-scale integration (LSI). Each vertically stacked chip is connected by a metal line that penetrates in Si that is called a TSV (Through Silicon Via). In the present study, the test element group (TEG) in the double-layered structure where a TSV was formed was made for trial purposes to develop elemental technology related to the correlation, design conditions, characteristics, and reliability that connected it to the stacking process conditions, and the thermal cycle test was executed. The junction disconnected by the thermal cycle test was observed, and the cause of the disconnection was presumed.

Thermal stress destruction analysis in low-k layer by via-last TSV structure

Investigation of the thermo-mechanical stress by using finite element analysis (FEA) and the destruction verification with thermal cycle (TC) test were carried out. It was found that the back end of line (BEOL) dielectric layer near the through silicon via (TSV) was cracked in case of a RT-400 °C heat cycle. Thermo-mechanical stress concentration at the TSV landing area has been confirmed by the results of FEA simulation. Dielectric layer cracking was caused at interface between the dielectric layer and edge corner of the land metal (M1) contact pad connected with the TSV. And the slit voids at the TSV sidewall were observed on the area of insufficient of side coverage of the titanium (Ti) metal barrier liner at the TSV bottom. The BEOL deformation of the metal contact area was also clear that the low-k cracks tend to occur at non constraint condition of the TSV sidewall as the slit void. In this paper shows that the interface becomes free surface as non-constrained condition caused by poor liner coverage, and it was insufficient interface adhesion to suppress the thermal expansion deformation of copper. This study provides that low-k layer cracking can be avoided by adopting optimized stress dispersion design to the BEOL low-k/copper with TSV landing pad structure.